公开(公告)号：US20230395184A1

公开(公告)日：2023-12-07

申请号：US17959191

申请日：2022-10-03

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Antonino Caprì ,  Daniele Balluchi ,  Massimiliano Patriarca

IPC: G11C29/52 ,  G11C11/4093 ,  G11C11/406

CPC classification number: G11C29/52 ,  G11C11/4093 ,  G11C11/40615

Abstract: A soft post package repair (sPPR) request is detected. Data stored in a target row of a memory array associated with the sPPR request is written to a buffer. Execution of non-maintenance requests on the target row is suspended. Responsive to suspension of execution of non-maintenance requests on the target row, the sPPR request is executed on the target row. Subsequent to completion of the sPPR request, execution of non-maintenance requests on the target row is resumed and the data stored in the buffer is written to the repaired target row.

公开(公告)号：US20250006248A1

公开(公告)日：2025-01-02

申请号：US18749370

申请日：2024-06-20

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Antonino Caprì

IPC: G11C11/408 ,  G11C11/4076

Abstract: Methods, systems, and devices related to row activation indication registers are disclosed. A first register can be coupled to a memory device and configured to store an indication of a first number of bit locations of a row address corresponding to the memory device to use in association with optimization of a row precharge time (tRP) of the memory device. A second register can be coupled to the memory device and configured to store an indication of a second number of bit locations of the row address to use in association with optimization of a row address to column address delay (tRCD) of the memory device.

公开(公告)号：US20240272831A1

公开(公告)日：2024-08-15

申请号：US18583540

申请日：2024-02-21

Applicant: Micron Technology, Inc.

Inventor： Nicola Del Gatto ,  Massimiliano Patriarca ,  Antonino Caprì ,  Emanuele Confalonieri ,  Angelo Alberto Rovelli

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0635 ,  G06F3/0656 ,  G06F3/0679

Abstract: Methods, systems, and devices for managed memory systems with multiple priority queues are described. Memory access commands may be received from a host and stored in a command queue. First and second subsets of the commands, respectively associated with first and second priorities, may be determined. The first and second subsets may be routed from the command queue to first and second queues, respectively. The first and second subsets may be processed from the first and second queues to third and fourth queues, respectively, at a storage controller, according to first and second processes that may be run concurrently according to parameters for prioritization between the first and second priorities. Data associated with the commands may be received from the host, temporarily stored in a buffer, then moved to a storage memory (for write commands) or retrieved from the storage memory, temporarily stored in the buffer, then transmitted to the host (for read commands).

公开(公告)号：US20220155997A1

公开(公告)日：2022-05-19

申请号：US16951985

申请日：2020-11-18

Applicant: Micron Technology, Inc.

Inventor： Nicola Del Gatto ,  Massimiliano Patriarca ,  Antonino Caprì ,  Emanuele Confalonieri ,  Angelo Alberto Rovelli

IPC: G06F3/06

Abstract: Methods, systems, and devices for managed memory systems with multiple priority queues are described. Memory access commands may be received from a host and stored in a command queue. First and second subsets of the commands, respectively associated with first and second priorities, may be determined. The first and second subsets may be routed from the command queue to first and second queues, respectively. The first and second subsets may be processed from the first and second queues to third and fourth queues, respectively, at a storage controller, according to first and second processes that may be run concurrently according to parameters for prioritization between the first and second priorities. Data associated with the commands may be received from the host, temporarily stored in a buffer, then moved to a storage memory (for write commands) or retrieved from the storage memory, temporarily stored in the buffer, then transmitted to the host (for read commands).

公开(公告)号：US12299331B2

公开(公告)日：2025-05-13

申请号：US18583540

申请日：2024-02-21

Applicant: Micron Technology, Inc.

Inventor： Nicola Del Gatto ,  Massimiliano Patriarca ,  Antonino Caprì ,  Emanuele Confalonieri ,  Angelo Alberto Rovelli

IPC: G06F3/06

Abstract: Methods, systems, and devices for managed memory systems with multiple priority queues are described. Memory access commands may be received from a host and stored in a command queue. First and second subsets of the commands, respectively associated with first and second priorities, may be determined. The first and second subsets may be routed from the command queue to first and second queues, respectively. The first and second subsets may be processed from the first and second queues to third and fourth queues, respectively, at a storage controller, according to first and second processes that may be run concurrently according to parameters for prioritization between the first and second priorities. Data associated with the commands may be received from the host, temporarily stored in a buffer, then moved to a storage memory (for write commands) or retrieved from the storage memory, temporarily stored in the buffer, then transmitted to the host (for read commands).

公开(公告)号：US20250130718A1

公开(公告)日：2025-04-24

申请号：US18889047

申请日：2024-09-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Antonino Caprì ,  Graziano Mirichigni ,  Marco Sforzin ,  Bryan David Kerstetter ,  John David Porter

IPC: G06F3/06

Abstract: A system performs operations including: storing a first value in a first memory location used for selecting a sub-channel of a plurality of sub-channels in a communication channel, each of the plurality of sub-channels corresponding to one or more memory components of a plurality of memory components of the memory device, wherein the first value specifies that a sub-channel selecting function is enabled; receiving, through the communication channel, a command directed to the memory device; responsive to receiving the command, storing a second value in a second memory location, wherein the second value is obtained from the command; determining that the second value matches a third value stored in a third memory location, wherein the third value stored in the third memory location comprises a preset value corresponding to a first component of the plurality of components of the memory device; and executing, by the first component, the command.

公开(公告)号：US11960770B2

公开(公告)日：2024-04-16

申请号：US17895041

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Simone Corbetta ,  Antonino Caprì ,  Emanuele Confalonieri

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0622 ,  G06F3/0683

Abstract: Systems, apparatuses, and methods related to access request management using sub-commands. Access requests received from a host system can be managed using a respective set of sub-commands corresponding to each access request and whose status can be tracked. Tracking how far access requests are processed at a fine granularity (of sub-commands) can provide efficient management of the access requests that can reduce a gap latency in processing multiple access requests.

公开(公告)号：US11914893B2

公开(公告)日：2024-02-27

申请号：US16951985

申请日：2020-11-18

Applicant: Micron Technology, Inc.

Inventor： Nicola Del Gatto ,  Massimiliano Patriarca ,  Antonino Caprì ,  Emanuele Confalonieri ,  Angelo Alberto Rovelli

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0635 ,  G06F3/0656 ,  G06F3/0679

Abstract: Methods, systems, and devices for managed memory systems with multiple priority queues are described. Memory access commands may be received from a host and stored in a command queue. First and second subsets of the commands, respectively associated with first and second priorities, may be determined. The first and second subsets may be routed from the command queue to first and second queues, respectively. The first and second subsets may be processed from the first and second queues to third and fourth queues, respectively, at a storage controller, according to first and second processes that may be run concurrently according to parameters for prioritization between the first and second priorities. Data associated with the commands may be received from the host, temporarily stored in a buffer, then moved to a storage memory (for write commands) or retrieved from the storage memory, temporarily stored in the buffer, then transmitted to the host (for read commands).

公开(公告)号：US20250069680A1

公开(公告)日：2025-02-27

申请号：US18949086

申请日：2024-11-15

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Antonino Caprì ,  Daniele Balluchi ,  Massimiliano Patriarca

IPC: G11C29/52 ,  G11C11/406 ,  G11C11/4093

Abstract: A soft post package repair (sPPR) request is detected. Data stored in a target row of a memory array associated with the sPPR request is written to a buffer. Execution of non-maintenance requests on the target row is suspended. Responsive to suspension of execution of non-maintenance requests on the target row, the sPPR request is executed on the target row. Subsequent to completion of the sPPR request, execution of non-maintenance requests on the target row is resumed and the data stored in the buffer is written to the repaired target row.

公开(公告)号：US20250068520A1

公开(公告)日：2025-02-27

申请号：US18777453

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Antonino Caprì ,  John Namkung

IPC: G06F11/10

Abstract: A row can be mapped to a spare row in memory. The mapping can include stopping the scheduler from issuing commands to the first bank. Responsive to stopping the scheduler from issuing commands to the first bank, the logic can map a particular row of the first bank to the spare row. The mapping can include allowing the scheduler to schedule commands for the second bank concurrently with the mapping of the particular row to the spare row.