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    MEMORY DEVICE DESERIALIZER CIRCUIT WITH A REDUCED FORM FACTOR
    1.
    发明申请
    MEMORY DEVICE DESERIALIZER CIRCUIT WITH A REDUCED FORM FACTOR 有权

    公开(公告)号：US20220392502A1

    公开(公告)日：2022-12-08

    申请号：US17340754

    申请日：2021-06-07

    Applicant: Micron Technology, Inc.

    Inventor： Guan Wang ,  Luigi Pilolli

    IPC: G11C7/22 ,  G11C7/10 ,  H03K3/356

    Abstract: A memory device including a memory array operatively coupled to an array data bus and a deserializer circuit operatively coupled with the array data bus. The deserializer circuit includes a first ring counter including a first set of flip-flops to sequentially output a set of rising edge clock signals based on a reference clock input and a second ring counter portion including a second set of flip-flop circuits to sequentially output a set of falling edge clock signals based on the reference clock input. A rising data circuit portion of the deserializer circuit includes a set of flip-flops that each receive a rising data portion from a respective latch circuit in response to a rising edge clock signal. A falling data circuit portion of the deserializer circuit includes a set of flip-flops that each receive a falling data portion from a respective latch circuit in response to a falling edge clock signal. The third set of flip-flops outputs the set of rising data portions and the fourth set of flip-flop circuits outputs the set of falling data portions to generate a synchronized data stream to output to the array data bus in response to a common clock signal.

    DATA BUS DUTY CYCLE DISTORTION COMPENSATION
    2.
    发明申请
    DATA BUS DUTY CYCLE DISTORTION COMPENSATION 有权

    公开(公告)号：US20220138120A1

    公开(公告)日：2022-05-05

    申请号：US16949510

    申请日：2020-10-30

    Applicant: Micron Technology, Inc.

    Inventor： Guan Wang ,  Ali Feiz Zarrin Ghalam ,  Chin-Yu Chen ,  Jongin Kim

    IPC: G06F13/16 ,  G11C16/32 ,  H03K3/017

    Abstract: An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.

    Internal clock distortion calibration using DC component offset of clock signal
    3.
    发明授权
    Internal clock distortion calibration using DC component offset of clock signal 有权

    公开(公告)号：US10972078B2

    公开(公告)日：2021-04-06

    申请号：US16920315

    申请日：2020-07-02

    Applicant: Micron Technology, Inc.

    Inventor： Guan Wang ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam

    IPC: G06F1/10 ,  H03K3/017 ,  H04L25/06 ,  H03K5/156 ,  G11C7/22 ,  G11C29/02 ,  H04L7/00 ,  H04L25/02 ,  G06F1/04

    Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock distortion calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.

    INTERNAL CLOCK DISTORTION CALIBRATION USING DC COMPONENT OFFSET OF CLOCK SIGNAL
    4.
    发明申请
    INTERNAL CLOCK DISTORTION CALIBRATION USING DC COMPONENT OFFSET OF CLOCK SIGNAL 审中-公开

    公开(公告)号：US20190190501A1

    公开(公告)日：2019-06-20

    申请号：US16204841

    申请日：2018-11-29

    Applicant: Micron Technology, Inc.

    Inventor： Guan Wang ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam

    IPC: H03K3/017 ,  G06F1/10 ,  H04L25/06 ,  G11C7/22 ,  H03K5/156

    Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.

    MEMORY DEVICE DESERIALIZER CIRCUIT WITH A REDUCED FORM FACTOR
    6.
    发明公开
    MEMORY DEVICE DESERIALIZER CIRCUIT WITH A REDUCED FORM FACTOR 审中-公开

    公开(公告)号：US20230162770A1

    公开(公告)日：2023-05-25

    申请号：US18097668

    申请日：2023-01-17

    Applicant: Micron Technology, Inc.

    Inventor： Guan Wang ,  Luigi Pilolli

    IPC: G11C7/22 ,  H03K3/356 ,  G11C7/10

    CPC classification number: G11C7/222 ,  H03K3/356095 ,  G11C7/1087 ,  G11C7/106

    Abstract: A memory sub-system including a memory device, wherein the memory device includes a circuit, operatively coupled to an array data bus of a memory array, and control logic, operatively coupled with the circuit, to perform operations including: deserializing a serial data stream in a first time domain to generate at least one of a set of rising data portions or a set of falling data portions; and synchronizing the at least one of the set of rising data portions or the set of falling data portions in a second time domain using at least one of a set of rising edge clock signals or a set of falling edge clock signals generated by a ring counter portion.

    Memory device deserializer circuit with a reduced form factor
    7.
    发明授权
    Memory device deserializer circuit with a reduced form factor 有权

    公开(公告)号：US11594268B2

    公开(公告)日：2023-02-28

    申请号：US17340754

    申请日：2021-06-07

    Applicant: Micron Technology, Inc.

    Inventor： Guan Wang ,  Luigi Pilolli

    IPC: G11C8/00 ,  G11C7/22 ,  H03K3/356 ,  G11C7/10

    Abstract: A memory device including a memory array operatively coupled to an array data bus and a deserializer circuit operatively coupled with the array data bus. The deserializer circuit includes a first ring counter including a first set of flip-flops to sequentially output a set of rising edge clock signals based on a reference clock input and a second ring counter portion including a second set of flip-flop circuits to sequentially output a set of falling edge clock signals based on the reference clock input. A rising data circuit portion of the deserializer circuit includes a set of flip-flops that each receive a rising data portion from a respective latch circuit in response to a rising edge clock signal. A falling data circuit portion of the deserializer circuit includes a set of flip-flops that each receive a falling data portion from a respective latch circuit in response to a falling edge clock signal. The third set of flip-flops outputs the set of rising data portions and the fourth set of flip-flop circuits outputs the set of falling data portions to generate a synchronized data stream to output to the array data bus in response to a common clock signal.

    Data bus duty cycle distortion compensation
    8.
    发明授权
    Data bus duty cycle distortion compensation 有权

    公开(公告)号：US11442877B2

    公开(公告)日：2022-09-13

    申请号：US16949510

    申请日：2020-10-30

    Applicant: Micron Technology, Inc.

    Inventor： Guan Wang ,  Ali Feiz Zarrin Ghalam ,  Chin-Yu Chen ,  Jongin Kim

    IPC: G06F13/36 ,  G06F13/16 ,  H03K3/017 ,  G11C16/32 ,  G11C16/04

    Abstract: An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.

    Internal clock distortion calibration using DC component offset of clock signal
    9.
    发明授权
    Internal clock distortion calibration using DC component offset of clock signal 有权

    公开(公告)号：US11336265B2

    公开(公告)日：2022-05-17

    申请号：US17214262

    申请日：2021-03-26

    Applicant: Micron Technology, Inc.

    Inventor： Guan Wang ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam

    IPC: G06F1/10 ,  H03K3/017 ,  H04L25/06 ,  H03K5/156 ,  G11C7/22 ,  G11C29/02 ,  H04L7/00 ,  H04L25/02 ,  G06F1/04

    Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock distortion calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.

    WRITE TRAINING IN MEMORY DEVICES
    10.
    发明申请
    WRITE TRAINING IN MEMORY DEVICES 有权

    公开(公告)号：US20210263660A1

    公开(公告)日：2021-08-26

    申请号：US17316956

    申请日：2021-05-11

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Luigi Pilolli ,  Ali Feiz Zarrin Ghalam ,  Guan Wang ,  Qiang Tang

    IPC: G06F3/06 ,  G11C16/32

    Abstract: A memory device includes a plurality of input/output (I/O) nodes, a circuit, a latch, a memory, and control logic. The plurality of I/O nodes receive a predefined data pattern. The circuit adjusts a delay for each I/O node as the predefined data pattern is received. The latch latches the data received on each I/O node. The memory stores the latched data. The control logic compares the stored latched data to an expected data pattern and sets the delay for each I/O node based on the comparison.

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