公开(公告)号：US20250069647A1

公开(公告)日：2025-02-27

申请号：US18749464

申请日：2024-06-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hirokazu Ato ,  Mamoru Nishizaki

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4097

Abstract: An example apparatus includes: first and second sense amplifier regions arranged such that the memory mat is sandwiched between the first and second sense amplifier regions in a first direction, the first and second sense amplifier regions including first and second sense amplifiers, respectively; and first and second array control circuit regions arranged in the first direction, the first and second array control circuit regions including first and second array control circuits configured to control the first and second sense amplifiers, respectively. Each of the first and second array control circuit regions includes a first well region in which a first circuit part of each of the first and second array control circuits are arranged, respectively. The first well region of the first array control circuit region and the first well region of the second array control circuit region are integrated.

公开(公告)号：US12254947B2

公开(公告)日：2025-03-18

申请号：US17893966

申请日：2022-08-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hirokazu Ato

IPC: G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: Apparatuses and methods including folded digit lines are disclosed. An example apparatus includes a first digit line portion extending in a first direction, a second digit line portion extending in the first direction, and a third digit line portion between the first and second digit line portions and extending in the first direction. A folded portion is coupled to the first and second digit line portions, and extends in a second direction and traverses the third digit line portion.

公开(公告)号：US20240177744A1

公开(公告)日：2024-05-30

申请号：US18481855

申请日：2023-10-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hirokazu Ato

IPC: G11C7/08 ,  G11C7/02 ,  G11C7/10

CPC classification number: G11C7/08 ,  G11C7/02 ,  G11C7/1048

Abstract: Apparatuses and methods including circuits in gap regions of a memory array are disclosed. An example apparatus includes first and second memory mats adjacent along a first direction, and further includes a region between the first and second memory mats along the first direction. The region includes a local input/output (LIO) line that extends along a second direction perpendicular to the first direction through the region, and further includes a LIO driver and a LIO precharge circuit coupled to the LIO line. The LIO driver is configured to drive the LIO line to data voltage levels based on data read from memory cells or based on data to be written to memory cells, and the LIO precharge circuit is configured to provide a LIO precharge voltage to the LIO lines.

公开(公告)号：US20240071426A1

公开(公告)日：2024-02-29

申请号：US17893966

申请日：2022-08-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hirokazu Ato

IPC: G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: G11C5/063 ,  H01L23/5223 ,  H01L23/528 ,  H01L23/53271

Abstract: Apparatuses and methods including folded digit lines are disclosed. An example apparatus includes a first digit line portion extending in a first direction, a second digit line portion extending in the first direction, and a third digit line portion between the first and second digit line portions and extending in the first direction. A folded portion is coupled to the first and second digit line portions, and extends in a second direction and traverses the third digit line portion.

公开(公告)号：US20200321278A1

公开(公告)日：2020-10-08

申请号：US16374418

申请日：2019-04-03

Applicant: Micron Technology, Inc.

Inventor： Hirokazu Ato ,  Koji Yasumori

IPC: H01L23/528 ,  H01L23/522

Abstract: Semiconductor devices may include a substrate and a redistribution layer. The redistribution layer may include a dielectric material and electrically conductive material. Vias may extend through the dielectric material. A first region of the electrically conductive material may be connected to a first subset of vias in a row from a first lateral side of the row, the first region occupying more than half of a width of the row on the first lateral side. A second region of the electrically conductive material may be connected to a second subset of vias in the row from a second, opposite lateral side of the row, the second region occupying more than half of the width of the row on the second lateral side.

公开(公告)号：US11031335B2

公开(公告)日：2021-06-08

申请号：US16374418

申请日：2019-04-03

Applicant: Micron Technology, Inc.

Inventor： Hirokazu Ato ,  Koji Yasumori

IPC: H01L23/52 ,  H01L23/528 ,  H01L23/522

Abstract: Semiconductor devices may include a substrate and a redistribution layer. The redistribution layer may include a dielectric material and electrically conductive material. Vias may extend through the dielectric material. A first region of the electrically conductive material may be connected to a first subset of vias in a row from a first lateral side of the row, the first region occupying more than half of a width of the row on the first lateral side. A second region of the electrically conductive material may be connected to a second subset of vias in the row from a second, opposite lateral side of the row, the second region occupying more than half of the width of the row on the second lateral side.