公开(公告)号：US20220406359A1

公开(公告)日：2022-12-22

申请号：US17350325

申请日：2021-06-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jacob Rice ,  Hiroshi Akamatsu

IPC: G11C11/4076 ,  G11C11/408

Abstract: An example apparatus may perform concurrent threshold voltage compensation in a memory array with distributed row redundancy. The example apparatus may include a row decoder configured to configured to, in response to a determination that the prime row address matches a defective prime row address, concurrently initiate a threshold voltage compensation operation on both of a prime row of the respective plurality of prime rows of memory cells of a first row section of the plurality of row sections corresponding to the prime row address and the respective redundant row of a second row section of the plurality of row sections. The row decoder may be further configured to stop an access operation associated with the prime row from proceeding based on a comparison of subset of match signals from either the first or second pluralities of row sections.

公开(公告)号：US20220406358A1

公开(公告)日：2022-12-22

申请号：US17350305

申请日：2021-06-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hiroshi Akamatsu ,  Wonjun Choi ,  Jacob Rice ,  Kenji Yoshida

IPC: G11C11/4076 ,  G11C11/408

Abstract: An example apparatus may perform concurrent threshold voltage compensation in a memory array with distributed row redundancy. The example apparatus may include a memory cell array having a mat having a plurality of row sections that each include respective prime memory cell rows and a respective redundant memory cell row. The example apparatus may further include a row decoder configured to receive an access command and a prime row address. The row decoder may be configured to, in response to a determination that the prime row address matches a defective prime row address, concurrently initiate a threshold voltage compensation operation on both of a prime row of the respective plurality of prime rows of memory cells of a first row section of the plurality of row sections corresponding to the prime row address and the respective redundant row of a second row section of the plurality of row sections.

公开(公告)号：US20240274720A1

公开(公告)日：2024-08-15

申请号：US18642326

申请日：2024-04-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hiroshi Akamatsu ,  Wonjun Choi ,  Jacob Rice ,  Kenji Yoshida

IPC: H01L29/786 ,  H01L29/20 ,  H01L29/66 ,  H01L29/737 ,  H01L29/74 ,  H10B12/00 ,  H10B53/30

CPC classification number: H01L29/78618 ,  H01L28/56 ,  H01L28/57 ,  H01L28/60 ,  H01L28/65 ,  H01L29/2003 ,  H01L29/6684 ,  H01L29/7375 ,  H01L29/7408 ,  H01L29/7869 ,  H10B53/30 ,  H10B12/312 ,  H10B12/36

Abstract: An example apparatus may perform concurrent threshold voltage compensation in a memory array with distributed row redundancy. The example apparatus may include a memory cell array having a mat having a plurality of row sections that each include respective prime memory cell rows and a respective redundant memory cell row. The example apparatus may further include a row decoder configured to receive an access command and a prime row address. The row decoder may be configured to, in response to a determination that the prime row address matches a defective prime row address, concurrently initiate a threshold voltage compensation operation on both of a prime row of the respective plurality of prime rows of memory cells of a first row section of the plurality of row sections corresponding to the prime row address and the respective redundant row of a second row section of the plurality of row sections.

公开(公告)号：US11967356B2

公开(公告)日：2024-04-23

申请号：US17350305

申请日：2021-06-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hiroshi Akamatsu ,  Wonjun Choi ,  Jacob Rice ,  Kenji Yoshida

IPC: G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/4076 ,  G11C11/4087

Abstract: An example apparatus may perform concurrent threshold voltage compensation in a memory array with distributed row redundancy. The example apparatus may include a memory cell array having a mat having a plurality of row sections that each include respective prime memory cell rows and a respective redundant memory cell row. The example apparatus may further include a row decoder configured to receive an access command and a prime row address. The row decoder may be configured to, in response to a determination that the prime row address matches a defective prime row address, concurrently initiate a threshold voltage compensation operation on both of a prime row of the respective plurality of prime rows of memory cells of a first row section of the plurality of row sections corresponding to the prime row address and the respective redundant row of a second row section of the plurality of row sections.

公开(公告)号：US11626154B2

公开(公告)日：2023-04-11

申请号：US17350325

申请日：2021-06-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jacob Rice ,  Hiroshi Akamatsu

IPC: G11C29/00 ,  G11C11/4076 ,  G11C11/408 ,  G11C29/50 ,  G11C29/44

Abstract: An example apparatus may perform concurrent threshold voltage compensation in a memory array with distributed row redundancy. The example apparatus may include a row decoder configured to configured to, in response to a determination that the prime row address matches a defective prime row address, concurrently initiate a threshold voltage compensation operation on both of a prime row of the respective plurality of prime rows of memory cells of a first row section of the plurality of row sections corresponding to the prime row address and the respective redundant row of a second row section of the plurality of row sections. The row decoder may be further configured to stop an access operation associated with the prime row from proceeding based on a comparison of subset of match signals from either the first or second pluralities of row sections.