公开(公告)号：US12108591B2

公开(公告)日：2024-10-01

申请号：US17458992

申请日：2021-08-27

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Yiming Zhu ,  Erxuan Ping

IPC: H10B12/00 ,  H01L29/06

CPC classification number: H10B12/312 ,  H01L29/0649 ,  H10B12/482

Abstract: A method for forming a semiconductor structure includes: providing a substrate, where a sacrificial layer and an active layer located on the sacrificial layer are formed on the substrate; patterning the active layer and the sacrificial layer to form a groove, where the active layer and the sacrificial layer are divided into a plurality of active regions by the groove; forming a first isolation layer surrounding the active regions in the groove; patterning the active layer in the active regions to form a plurality of separate active patterns, where at least one of side walls or ends of the active patterns is connected to the first isolation layer; removing the sacrificial layer along an opening located between two adjacent one of the active patterns to form a gap between a bottom of the active patterns and the semiconductor substrate; and forming a bit line in the gap.

公开(公告)号：US20240282171A1

公开(公告)日：2024-08-22

申请号：US18588209

申请日：2024-02-27

Applicant: Everi Payments Inc.

Inventor： Adam Fong ,  Michael Elston

IPC: G07F17/32 ,  A01D41/127 ,  A01D41/14 ,  A63F13/71 ,  G06Q50/02 ,  H01L23/522 ,  H01L23/528 ,  H10B12/00

CPC classification number: G07F17/3244 ,  A01D41/1274 ,  A01D41/141 ,  A01D41/145 ,  A63F13/71 ,  G06Q50/02 ,  G07F17/3218 ,  G07F17/3225 ,  H01L23/5226 ,  H01L23/5283 ,  H10B12/312 ,  H10B12/50

Abstract: Relative to a gaming system, a jackpot or game win processing device and server are configured to receive acknowledgement from a player regarding a gaming win award, such as input to the game win processing device of a signature by the player to gaming win forms. In response, the server is configured to generate at least one gaming win reporting form, such as a W2G, to store that form and provide access to the form, such as by emailing the form to the player or allowing the player to access the form via a portal.

公开(公告)号：US11922764B2

公开(公告)日：2024-03-05

申请号：US18077019

申请日：2022-12-07

Applicant: Everi Payments Inc.

Inventor： Adam Fong ,  Michael Elston

IPC: G07F17/32 ,  A01D41/127 ,  A01D41/14 ,  A63F13/71 ,  G06Q50/02 ,  H01L23/522 ,  H01L23/528 ,  H10B12/00

CPC classification number: G07F17/3244 ,  A01D41/1274 ,  A01D41/141 ,  A01D41/145 ,  A63F13/71 ,  G06Q50/02 ,  G07F17/3218 ,  G07F17/3225 ,  H01L23/5226 ,  H01L23/5283 ,  H10B12/312 ,  H10B12/50

Abstract: Relative to a gaming system, a jackpot or game win processing device and server are configured to receive acknowledgement from a player regarding a gaming win award, such as input to the game win processing device of a signature by the player to gaming win forms. In response, the server is configured to generate at least one gaming win reporting form, such as a W2G, to store that form and provide access to the form, such as by emailing the form to the player or allowing the player to access the form via a portal.

公开(公告)号：US11916149B2

公开(公告)日：2024-02-27

申请号：US17814330

申请日：2022-07-22

Applicant: Kepler Computing Inc.

Inventor： Ramesh Ramamoorthy ,  Sasikanth Manipatruni ,  Gaurav Thareja

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/20 ,  H01L29/74 ,  H01L29/737 ,  H10B53/30 ,  H10B12/00 ,  H01L49/02

CPC classification number: H01L29/78618 ,  H01L28/56 ,  H01L28/57 ,  H01L28/60 ,  H01L28/65 ,  H01L29/2003 ,  H01L29/6684 ,  H01L29/7375 ,  H01L29/7408 ,  H01L29/7869 ,  H10B53/30 ,  H10B12/312 ,  H10B12/36

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a transistor formed on a silicon substrate and a capacitor electrically connected to the transistor by a conductive via. The capacitor comprises upper and lower conductive oxide electrodes on opposing sides of a polar layer, wherein the lower conductive oxide electrode is electrically connected to a drain of the transistor. The capacitor additionally comprises a polar layer comprising a base polar material doped with a dopant, wherein the base polar material includes one or more metal elements and one or both of oxygen or nitrogen, wherein the dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The semiconductor device additionally comprises a lower barrier layer comprising a refractory metal or an intermetallic compound between the lower conductive oxide electrode and the conductive via.

公开(公告)号：US11757043B2

公开(公告)日：2023-09-12

申请号：US17819601

申请日：2022-08-12

Applicant: Kepler Computing Inc.

Inventor： Ramesh Ramamoorthy ,  Sasikanth Manipatruni ,  Gaurav Thareja

IPC: H01L29/00 ,  H01L29/786 ,  H01L29/66 ,  H01L29/20 ,  H01L29/74 ,  H01L29/737 ,  H01L49/02 ,  H10B53/30 ,  H10B12/00

CPC classification number: H01L29/78618 ,  H01L28/56 ,  H01L28/57 ,  H01L28/65 ,  H01L29/2003 ,  H01L29/6684 ,  H01L29/7375 ,  H01L29/7408 ,  H01L29/7869 ,  H10B53/30 ,  H10B12/312 ,  H10B12/36

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.

公开(公告)号：US20240292600A1

公开(公告)日：2024-08-29

申请号：US18240516

申请日：2023-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Tae RYU ,  Byong-Deok CHOI ,  Sungwon YOO ,  Wonsok LEE ,  Yongsang YOO

IPC: H10B12/00 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

CPC classification number: H10B12/482 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  H01L28/90 ,  H10B12/312 ,  H10B12/315 ,  H10B12/50

Abstract: A memory device includes a first memory cell connected to a first bitline and a second memory cell connected to a second bitline, wherein the first memory cell may include a first access transistor including one end connected to the first bitline, and a first capacitor including one electrode connected to another end of the first access transistor and another electrode connected to the second bitline, and the first access transistor may include an oxide semiconductor.

公开(公告)号：US20240274720A1

公开(公告)日：2024-08-15

申请号：US18642326

申请日：2024-04-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hiroshi Akamatsu ,  Wonjun Choi ,  Jacob Rice ,  Kenji Yoshida

IPC: H01L29/786 ,  H01L29/20 ,  H01L29/66 ,  H01L29/737 ,  H01L29/74 ,  H10B12/00 ,  H10B53/30

CPC classification number: H01L29/78618 ,  H01L28/56 ,  H01L28/57 ,  H01L28/60 ,  H01L28/65 ,  H01L29/2003 ,  H01L29/6684 ,  H01L29/7375 ,  H01L29/7408 ,  H01L29/7869 ,  H10B53/30 ,  H10B12/312 ,  H10B12/36

Abstract: An example apparatus may perform concurrent threshold voltage compensation in a memory array with distributed row redundancy. The example apparatus may include a memory cell array having a mat having a plurality of row sections that each include respective prime memory cell rows and a respective redundant memory cell row. The example apparatus may further include a row decoder configured to receive an access command and a prime row address. The row decoder may be configured to, in response to a determination that the prime row address matches a defective prime row address, concurrently initiate a threshold voltage compensation operation on both of a prime row of the respective plurality of prime rows of memory cells of a first row section of the plurality of row sections corresponding to the prime row address and the respective redundant row of a second row section of the plurality of row sections.

公开(公告)号：US20240224509A1

公开(公告)日：2024-07-04

申请号：US18177766

申请日：2023-03-03

Applicant: Powerchip Semiconductor Manufacturing Corporation

Inventor： Wen-Yueh Chang

IPC: H10B12/00 ,  H01L25/16 ,  H01L29/786 ,  H10B80/00

CPC classification number: H10B12/395 ,  H01L25/16 ,  H01L29/7869 ,  H01L29/78696 ,  H10B12/0383 ,  H10B12/053 ,  H10B12/312 ,  H10B12/482 ,  H10B12/488 ,  H10B80/00

Abstract: A dynamic random access memory device and a method for forming the same are provided. The dynamic random access memory device includes a substrate, multiple word lines, multiple bit lines, and multiple memory device layers. The word lines extend toward a first direction. The bit lines extend toward a second direction. The second direction is orthogonal to the first direction. The memory device layers are disposed on the substrate and stacked in a normal direction of the substrate. Each memory device layers includes multiple memory cells and a capacitor voltage transmission line. The memory cells include a thin film transistor and a capacitor. Each memory cells is electrically connected to a corresponding word line and a corresponding bit line. The capacitor voltage transmission line is electrically connected to the capacitor. The word lines or the bit lines extend in a same direction as the capacitor voltage transmission line.

公开(公告)号：US20240074151A1

公开(公告)日：2024-02-29

申请号：US18456383

申请日：2023-08-25

Applicant: Kioxia Corporation

Inventor： Takao KOSAKA

IPC: H10B12/00

CPC classification number: H10B12/33 ,  H10B12/312 ,  H10B12/482 ,  H10B12/488

Abstract: According to one embodiment, a semiconductor device includes a conductive layer, an oxide semiconductor layer provided penetrating the conductive layer in a first direction, and a first insulating film provided between the conductive layer and the oxide semiconductor layer in a second direction that intersects the first direction. The first insulating film comprises boron nitride.

公开(公告)号：US20240049458A1

公开(公告)日：2024-02-08

申请号：US18226159

申请日：2023-07-25

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Zhiyong Cai ,  Ziyu Zhang ,  Kang Yang ,  Hsing-An Lo ,  Yi Zhou

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/312 ,  H10B12/482 ,  H10B12/05

Abstract: Three-dimensional (3D) semiconductor devices and fabricating methods are provided. In some implementations, a disclosed semiconductor device comprises: an array of vertical transistors each comprising a semiconductor body extending in a vertical direction; a plurality of word lines each extending along a first lateral direction and comprising a plurality of gate structures of a row of the array of vertical transistors arranged in the first lateral direction; and a plurality of bit lines each extending along a second lateral direction different from the first lateral direction and comprising silicide.