公开(公告)号：US20240071500A1

公开(公告)日：2024-02-29

申请号：US18234046

申请日：2023-08-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jae Kyu Choi ,  Jin Yue ,  Kyubong Jung ,  Albert Fayrushin ,  Jae Young Ahn ,  Jun Kyu Yang

IPC: G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Memory array structures, and methods of their formation, might include a first memory cell having a first control gate and an adjacent first portion of a charge-blocking structure, a second memory cell having a second control gate and an adjacent second portion of the charge-blocking structure, and a first dielectric material between the first control gate and the second control gate, and adjacent to a third portion of the charge-blocking structure that is between the first and second portions of the charge-blocking structure. The third portion of the charge-blocking structure might include a second dielectric material and a third dielectric material different than the second dielectric material, and the first portion of the charge-blocking structure and the second portion of the charge-blocking structure might each include the third dielectric material and a fourth dielectric material different than the second dielectric material. Apparatus might include such memory array structures.