公开(公告)号：US20240347128A1

公开(公告)日：2024-10-17

申请号：US18753389

申请日：2024-06-25

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Akira Goda ,  Dave Scott Ebsen ,  Lakshmi Kalpana Vakati ,  Jiangli Zhu ,  Peter Feeley ,  Sanjay Subbarao ,  Vivek Shivhare ,  Fangfang Zhu

IPC: G11C29/52 ,  G11C29/02

CPC classification number: G11C29/52 ,  G11C29/022

Abstract: Methods, systems, and apparatuses include retrieving a defectivity footprint of a portion of memory, the portion of memory composed of multiple blocks. A deck programming order is determined, based on the defectivity footprint, for a current block of the multiple blocks. The current block is composed of multiple decks. The deck programming order is an order in which the multiple decks are programmed. The multiple decks programmed according to the determined deck programming order.

公开(公告)号：US20240248646A1

公开(公告)日：2024-07-25

申请号：US18623881

申请日：2024-04-01

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Eric N. Lee ,  Jeffrey S. McNeil ,  Jonathan S. Parry ,  Lakshmi Kalpana Vakati

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679

Abstract: A method performed by a processing device receives a plurality of write operation requests, where each of the write operation requests specifies a respective one of the memory units, identifies one or more operating characteristic values, where each operating characteristic value reflects one or more memory access operations performed on a memory device, and determines whether the operating characteristic values satisfy one or more threshold criteria. Responsive to determining that the operating characteristic values satisfy the one or more threshold criteria, the method performs a plurality of write operations, where each of the write operations writes data to the respective one of the memory units, and performs a multiple-read scan operation subsequent to the plurality of write operations, where the multiple-read scan operation reads data from each of the memory units.

公开(公告)号：US20240393980A1

公开(公告)日：2024-11-28

申请号：US18792881

申请日：2024-08-02

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Peter Feeley ,  Jiangli Zhu ,  Fangfang Zhu ,  Akira Goda ,  Lakshmi Kalpana Vakati ,  Vivek Shivhare ,  Dave Scott Ebsen ,  Sanjay Subbarao

IPC: G06F3/06

Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first block and a second block. A buffer is allocated for executing the write command to the first block. The buffer includes multiple buffer decks and the buffer holds the user data written to the first block. User data is programmed into the first block to a threshold percentage. The threshold percentage is less than one hundred percent of the first block. A buffer deck is invalidated in response to programming the first block to the threshold percentage. The buffer deck is reallocated to the second block for programming the user data into the second block. The buffer deck holds user data written to the second block.

公开(公告)号：US12001721B2

公开(公告)日：2024-06-04

申请号：US17882355

申请日：2022-08-05

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Lakshmi Kalpana Vakati ,  Dave Scott Ebsen ,  Peter Feeley ,  Sanjay Subbarao ,  Vivek Shivhare ,  Jiangli Zhu ,  Fangfang Zhu ,  Akira Goda

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0683

Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second block are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. The temporary parity data is maintained in the buffer until a second programming pass of the first and second block.

公开(公告)号：US20240045616A1

公开(公告)日：2024-02-08

申请号：US17882355

申请日：2022-08-05

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Lakshmi Kalpana Vakati ,  Dave Scott Ebsen ,  Peter Feeley ,  Sanjay Subbarao ,  Vivek Shivhare ,  Jiangli Zhu ,  Fangfang Zhu ,  Akira Goda

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0656 ,  G06F3/064 ,  G06F3/0619 ,  G06F3/0683

Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second block are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. The temporary parity data is maintained in the buffer until a second programming pass of the first and second block.

公开(公告)号：US20250110841A1

公开(公告)日：2025-04-03

申请号：US18980708

申请日：2024-12-13

Applicant: Micron Technology, Inc.

Inventor： Lu Tong ,  Ashish Ghai ,  Chai Chuan Yao ,  Ekamdeep Singh ,  Lakshmi Kalpana Vakati ,  Sheng Huang Lee ,  Matthew Ivan Warren ,  Dheeraj Srinivasan ,  Jeffrey Ming-Hung Tsai

IPC: G06F11/20 ,  G06F3/06

Abstract: Control logic in a memory device executes a programming operation to program the set of memory blocks of the set of memory planes to a set of a programming levels. The control logic identify a subset of memory blocks of one or more memory planes that pass a program count operation associated with a last programming level of the set of programming levels. The control logic further terminates execution of the programming operation on the one or more memory planes associated with the subset of memory blocks.

公开(公告)号：US12204422B2

公开(公告)日：2025-01-21

申请号：US18143937

申请日：2023-05-05

Applicant: Micron Technology, Inc.

Inventor： Lu Tong ,  Ashish Ghai ,  Chai Chuan Yao ,  Ekamdeep Singh ,  Lakshmi Kalpana Vakati ,  Sheng Huang Lee ,  Matthew Ivan Warren ,  Dheeraj Srinivasan ,  Jeffrey Ming-Hung Tsai

IPC: G06F11/20 ,  G06F3/06

Abstract: Control logic in a memory device executes a programming operation to program the set of memory blocks of the set of memory planes to a set of a programming levels. In response to determining at least a portion of a first memory block passed a program verify operation associated with a last programming level of the set of programming levels, the control logic executes a first program sub-operation to terminate the programming operation with respect to a first subset of one or more memory planes of the set of memory planes that passed the program verify operation associated with the last programming level and identify a second subset of one or more memory planes that failed the program verify operation associated with the last programming level. The control logic executes a second program sub-operation to apply a trim set to the second subset of one or more memory planes that failed the program verify operation of the last programming level.

公开(公告)号：US20240220110A1

公开(公告)日：2024-07-04

申请号：US18540716

申请日：2023-12-14

Applicant: Micron Technology, Inc.

Inventor： Sheng-Huang Lee ,  Lu Tong ,  Lawrence Celso Miranda ,  Lakshmi Kalpana Vakati ,  Ekamdeep Singh ,  Ashish Ghai

IPC: G06F3/06 ,  G06F11/07

CPC classification number: G06F3/061 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/0754

Abstract: Control logic in a memory device identifies a segment of the plurality of segments of a memory array of a memory device, and determines a health status for the segment from a plurality of possible health statuses, the plurality of possible health statuses comprising three or more health statuses. The control logic further provides the health status for the segment to a memory sub-system controller associated with the memory device, wherein the memory sub-system controller is to perform a corresponding action with respect to the segment based on the health status, and wherein the corresponding action is different for each of the plurality of possible health statuses.

公开(公告)号：US20240029815A1

公开(公告)日：2024-01-25

申请号：US17872567

申请日：2022-07-25

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Akira Goda ,  Dave Scott Ebsen ,  Lakshmi Kalpana Vakati ,  Jiangli Zhu ,  Peter Feeley ,  Sanjay Subbarao ,  Vivek Shivhare ,  Fangfang Zhu

IPC: G11C29/52 ,  G11C29/02

CPC classification number: G11C29/52 ,  G11C29/022

Abstract: Methods, systems, and apparatuses include retrieving a defectivity footprint of a portion of memory, the portion of memory composed of multiple blocks. A deck programming order is determined, based on the defectivity footprint, for a current block of the multiple blocks. The current block is composed of multiple decks. The deck programming order is an order in which the multiple decks are programmed. The multiple decks programmed according to the determined deck programming order.

公开(公告)号：US20240302999A1

公开(公告)日：2024-09-12

申请号：US18651590

申请日：2024-04-30

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Lakshmi Kalpana Vakati ,  Dave Scott Ebsen ,  Peter Feeley ,  Sanjay Subbarao ,  Vivek Shivhare ,  Jiangli Zhu ,  Fangfang Zhu ,  Akira Goda

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0683

Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second block are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. The temporary parity data is maintained in the buffer until a second programming pass of the first and second block.