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1.发明申请公开(公告)号：US20250110841A1
公开(公告)日：2025-04-03
申请号：US18980708
申请日：2024-12-13
Applicant: Micron Technology, Inc.
Inventor： Lu Tong , Ashish Ghai , Chai Chuan Yao , Ekamdeep Singh , Lakshmi Kalpana Vakati , Sheng Huang Lee , Matthew Ivan Warren , Dheeraj Srinivasan , Jeffrey Ming-Hung Tsai
Abstract: Control logic in a memory device executes a programming operation to program the set of memory blocks of the set of memory planes to a set of a programming levels. The control logic identify a subset of memory blocks of one or more memory planes that pass a program count operation associated with a last programming level of the set of programming levels. The control logic further terminates execution of the programming operation on the one or more memory planes associated with the subset of memory blocks.
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2.发明授权公开(公告)号：US12204422B2
公开(公告)日：2025-01-21
申请号：US18143937
申请日：2023-05-05
Applicant: Micron Technology, Inc.
Inventor： Lu Tong , Ashish Ghai , Chai Chuan Yao , Ekamdeep Singh , Lakshmi Kalpana Vakati , Sheng Huang Lee , Matthew Ivan Warren , Dheeraj Srinivasan , Jeffrey Ming-Hung Tsai
Abstract: Control logic in a memory device executes a programming operation to program the set of memory blocks of the set of memory planes to a set of a programming levels. In response to determining at least a portion of a first memory block passed a program verify operation associated with a last programming level of the set of programming levels, the control logic executes a first program sub-operation to terminate the programming operation with respect to a first subset of one or more memory planes of the set of memory planes that passed the program verify operation associated with the last programming level and identify a second subset of one or more memory planes that failed the program verify operation associated with the last programming level. The control logic executes a second program sub-operation to apply a trim set to the second subset of one or more memory planes that failed the program verify operation of the last programming level.
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公开(公告)号：US20240220110A1
公开(公告)日：2024-07-04
申请号：US18540716
申请日：2023-12-14
Applicant: Micron Technology, Inc.
Inventor： Sheng-Huang Lee , Lu Tong , Lawrence Celso Miranda , Lakshmi Kalpana Vakati , Ekamdeep Singh , Ashish Ghai
CPC classification number: G06F3/061 , G06F3/0653 , G06F3/0679 , G06F11/073 , G06F11/0754
Abstract: Control logic in a memory device identifies a segment of the plurality of segments of a memory array of a memory device, and determines a health status for the segment from a plurality of possible health statuses, the plurality of possible health statuses comprising three or more health statuses. The control logic further provides the health status for the segment to a memory sub-system controller associated with the memory device, wherein the memory sub-system controller is to perform a corresponding action with respect to the segment based on the health status, and wherein the corresponding action is different for each of the plurality of possible health statuses.
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Patent Agency Ranking
公开(公告)号：US20220066894A1
公开(公告)日：2022-03-03
申请号：US17396083
申请日：2021-08-06
Applicant: Micron Technology, Inc.
Inventor： Sri Rama Namala , Lu Tong , Kristopher Kopel , Sheng-Huang Lee , Chang H. Siau
Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).
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5.发明公开公开(公告)号：US20230367680A1
公开(公告)日：2023-11-16
申请号：US18143937
申请日：2023-05-05
Applicant: Micron Technology, Inc.
Inventor： Lu Tong , Ashish Ghai , Chai Chuan Yao , Ekamdeep Singh , Lakshmi Kalpana Vakati , Sheng Huang Lee , Matthew Ivan Warren , Dheeraj Srinivasan , Jeffrey Ming-Hung Tsai
CPC classification number: G06F11/2023 , G06F3/0617 , G06F3/064 , G06F3/0673 , G06F2201/805
Abstract: Control logic in a memory device executes a programming operation to program the set of memory blocks of the set of memory planes to a set of a programming levels. In response to determining at least a portion of a first memory block passed a program verify operation associated with a last programming level of the set of programming levels, the control logic executes a first program sub-operation to terminate the programming operation with respect to a first subset of one or more memory planes of the set of memory planes that passed the program verify operation associated with the last programming level and identify a second subset of one or more memory planes that failed the program verify operation associated with the last programming level. The control logic executes a second program sub-operation to apply a trim set to the second subset of one or more memory planes that failed the program verify operation of the last programming level.
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公开(公告)号：US11537484B2
公开(公告)日：2022-12-27
申请号：US17396083
申请日：2021-08-06
Applicant: Micron Technology, Inc.
Inventor： Sri Rama Namala , Lu Tong , Kristopher Kopel , Sheng-Huang Lee , Chang H. Siau
Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).
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公开(公告)号：US12007860B2
公开(公告)日：2024-06-11
申请号：US18075958
申请日：2022-12-06
Applicant: Micron Technology, Inc.
Inventor： Sri Rama Namala , Lu Tong , Kristopher Kopel , Sheng-Huang Lee , Chang H. Siau
CPC classification number: G06F11/2094 , G11C16/0483 , G06F2201/85 , G11C16/26
Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).
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公开(公告)号：US20230111510A1
公开(公告)日：2023-04-13
申请号：US18075958
申请日：2022-12-06
Applicant: Micron Technology, Inc.
Inventor： Sri Rama Namala , Lu Tong , Kristopher Kopel , Sheng-Huang Lee , Chang H. Siau
Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).
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