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    APPARATUSES INCLUDING MULTIPLE CHANNEL MATERIALS WITHIN A TIER STACK
    3.
    发明申请
    APPARATUSES INCLUDING MULTIPLE CHANNEL MATERIALS WITHIN A TIER STACK 有权

    公开(公告)号：US20220359767A1

    公开(公告)日：2022-11-10

    申请号：US17814164

    申请日：2022-07-21

    Applicant: Micron Technology, Inc.

    Inventor： Akira Goda ,  Marc Aoulaiche

    IPC: H01L29/786 ,  H01L29/267 ,  H01L27/11556 ,  H01L29/66 ,  H01L29/10

    Abstract: An apparatus comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, a first channel material extending vertically through the stack, and a second channel material adjacent the first channel material and extending vertically through the stack. The first channel material has a first band gap and the second channel material has a second band gap that is relatively larger than the first band gap. The apparatus further comprises a conductive plug structure adjacent to each of the first channel material and the second channel material, and a conductive line structure adjacent to the conductive plug structure. Methods of forming the apparatus, memory devices, and electronic systems are also described.

    Memory devices including gate leakage transistors
    6.
    发明授权
    Memory devices including gate leakage transistors 有权

    公开(公告)号：US11869590B2

    公开(公告)日：2024-01-09

    申请号：US17458954

    申请日：2021-08-27

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Andrew Bicksler ,  Marc Aoulaiche

    IPC: G11C16/04 ,  G11C16/16 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

    CPC classification number: G11C16/0483 ,  G11C16/16 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

    Abstract: A memory device includes a string of series-connected memory cells, a data line, a first select transistor, a common source, a second select transistor, and a gate leakage transistor. The string of series-connected memory cells includes a vertical channel region. Each memory cell of the string of series-connected memory cells includes a first gate stack structure. The data line is connected to the vertical channel region. The first select transistor is connected between the data line and the string of series-connected memory cells. The second select transistor is connected between the common source and the string of series-connected memory cells. The gate leakage transistor is connected between the first select transistor and the second select transistor. The gate leakage transistor includes a second gate stack structure different from the first gate stack structure.

    MEMORY DEVICES INCLUDING GATE LEAKAGE TRANSISTORS
    7.
    发明申请
    MEMORY DEVICES INCLUDING GATE LEAKAGE TRANSISTORS 有权

    公开(公告)号：US20230065743A1

    公开(公告)日：2023-03-02

    申请号：US17458954

    申请日：2021-08-27

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Andrew Bicksler ,  Marc Aoulaiche

    IPC: G11C16/04 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/16

    Abstract: A memory device includes a string of series-connected memory cells, a data line, a first select transistor, a common source, a second select transistor, and a gate leakage transistor. The string of series-connected memory cells includes a vertical channel region. Each memory cell of the string of series-connected memory cells includes a first gate stack structure. The data line is connected to the vertical channel region. The first select transistor is connected between the data line and the string of series-connected memory cells. The second select transistor is connected between the common source and the string of series-connected memory cells. The gate leakage transistor is connected between the first select transistor and the second select transistor. The gate leakage transistor includes a second gate stack structure different from the first gate stack structure.

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