公开(公告)号：US09136331B2

公开(公告)日：2015-09-15

申请号：US13860427

申请日：2013-04-10

Applicant: Micron Technology, Inc.

Inventor： Chris Larsen ,  Alex J. Schrinsky ,  John D. Hopkins ,  Matthew King

IPC: H01L29/06 ,  H01L21/76

CPC classification number: H01L29/0657 ,  H01L21/743 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0692

Abstract: Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X.

Abstract translation: 一些实施例包括具有通过至少一个虚拟突起彼此间隔开的两个台面的半导体材料的半导体结构。 虚拟突起具有沿X的横截面的宽度，并且台面具有至少3X的横截面的宽度。 一些实施例包括具有存储器阵列区域和与存储器阵列区域相邻的外围区域的半导体结构。 周边区域内的半导体材料被图案化成两个相对较宽的台面，其彼此间隔开至少一个较窄的突起。 相对窄的突起具有沿X的横截面的宽度，并且相对宽的台面具有至少3X的横截面的宽度。

公开(公告)号：US20240315028A1

公开(公告)日：2024-09-19

申请号：US18604200

申请日：2024-03-13

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Aaron S. Yip ,  Giovanni Mazzone ,  Matthew King

IPC: H10B43/27 ,  G11C16/04 ,  G11C16/10 ,  H10B41/27

CPC classification number: H10B43/27 ,  G11C16/0483 ,  G11C16/10 ,  H10B41/27

Abstract: A system for manufacturing a memory device forms a memory array comprising a plurality of memory cells arranged in a plurality of memory strings along a plurality of memory array pillars, wherein respective subsets of the memory array pillars correspond to respective sub-blocks of a block of the memory array, and forms a plurality of deintegrated source segments adjacent to the memory array, wherein the source segments of the plurality of deintegrated source segments are associated with respective sub-blocks and are physically segregated from one another.

公开(公告)号：US20140306323A1

公开(公告)日：2014-10-16

申请号：US13860427

申请日：2013-04-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chris Larsen ,  Alex J. Schrinsky ,  John D. Hopkins ,  Matthew King

IPC: H01L29/06

CPC classification number: H01L29/0657 ,  H01L21/743 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0692

Abstract: Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X.

Abstract translation: 一些实施例包括具有通过至少一个虚拟突起彼此间隔开的两个台面的半导体材料的半导体结构。 虚拟突起具有沿X的横截面的宽度，并且台面具有至少3X的横截面的宽度。 一些实施例包括具有存储器阵列区域和与存储器阵列区域相邻的外围区域的半导体结构。 周边区域内的半导体材料被图案化成两个相对较宽的台面，其彼此间隔开至少一个较窄的突起。 相对窄的突起具有沿X的横截面的宽度，并且相对宽的台面具有至少3X的横截面的宽度。