公开(公告)号：US20190378843A1

公开(公告)日：2019-12-12

申请号：US16419978

申请日：2019-05-22

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Mohd Kamran Akhtar ,  Silvia Borsari ,  Alex J. Schrinsky

IPC: H01L27/108

Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.

公开(公告)号：US11139309B2

公开(公告)日：2021-10-05

申请号：US16503178

申请日：2019-07-03

Applicant: Micron Technology, Inc.

Inventor： Kamal Kumar Muthukrishnan ,  Alex J. Schrinsky

IPC: H01L27/11502 ,  G11C11/22 ,  H01L27/108 ,  H01L29/51

Abstract: Integrated circuitry comprises a plurality of features horizontally arrayed in a two-dimensional (2D) lattice. The 2D lattice comprises a parallelogram unit cell having four lattice points and four straight-line sides between pairs of the four lattice points. The parallelogram unit cell has a straight-line diagonal there-across between two diagonally-opposed of the four lattice points. The straight-line diagonal is longer than each of the four straight-line sides. Individual of the features are at one of the four lattice points and occupy a maximum horizontal area that is horizontally elongated along a direction that is horizontally angled relative to each of the four straight-line sides. Other embodiments, including methods, are disclosed.

公开(公告)号：US20210005619A1

公开(公告)日：2021-01-07

申请号：US16503178

申请日：2019-07-03

Applicant: Micron Technology, Inc.

Inventor： Kamal Kumar Muthukrishnan ,  Alex J. Schrinsky

IPC: H01L27/11502 ,  G11C11/22 ,  H01L29/51 ,  H01L27/108

Abstract: Integrated circuitry comprises a plurality of features horizontally arrayed in a two-dimensional (2D) lattice. The 2D lattice comprises a parallelogram unit cell having four lattice points and four straight-line sides between pairs of the four lattice points. The parallelogram unit cell has a straight-line diagonal there-across between two diagonally-opposed of the four lattice points. The straight-line diagonal is longer than each of the four straight-line sides. Individual of the features are at one of the four lattice points and occupy a maximum horizontal area that is horizontally elongated along a direction that is horizontally angled relative to each of the four straight-line sides. Other embodiments, including methods, are disclosed

公开(公告)号：US20200286898A1

公开(公告)日：2020-09-10

申请号：US16880900

申请日：2020-05-21

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Mohd Kamran Akhtar ,  Silvia Borsari ,  Alex J. Schrinsky

IPC: H01L27/108

Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.

公开(公告)号：US20180019245A1

公开(公告)日：2018-01-18

申请号：US15652724

申请日：2017-07-18

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Russell A. Benson ,  Brent Gilgen ,  Alex J. Schrinsky ,  Sanh D. Tang ,  Si-Woo Lee

IPC: H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10885 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76877 ,  H01L27/10814 ,  H01L27/10855

Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.

公开(公告)号：US09136331B2

公开(公告)日：2015-09-15

申请号：US13860427

申请日：2013-04-10

Applicant: Micron Technology, Inc.

Inventor： Chris Larsen ,  Alex J. Schrinsky ,  John D. Hopkins ,  Matthew King

IPC: H01L29/06 ,  H01L21/76

CPC classification number: H01L29/0657 ,  H01L21/743 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0692

Abstract: Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X.

Abstract translation: 一些实施例包括具有通过至少一个虚拟突起彼此间隔开的两个台面的半导体材料的半导体结构。 虚拟突起具有沿X的横截面的宽度，并且台面具有至少3X的横截面的宽度。 一些实施例包括具有存储器阵列区域和与存储器阵列区域相邻的外围区域的半导体结构。 周边区域内的半导体材料被图案化成两个相对较宽的台面，其彼此间隔开至少一个较窄的突起。 相对窄的突起具有沿X的横截面的宽度，并且相对宽的台面具有至少3X的横截面的宽度。

公开(公告)号：US11877434B2

公开(公告)日：2024-01-16

申请号：US16924995

申请日：2020-07-09

Applicant: Micron Technology, Inc.

Inventor： Yan Li ,  Song Guo ,  Mohd Kamran Akhtar ,  Alex J. Schrinsky

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H10B12/00 ,  H01L21/3065

CPC classification number: H10B12/053 ,  H01L21/3065 ,  H10B12/34

Abstract: A method of forming a microelectronic device structure comprises exposing a silicon structure to an etching chemistry at a first bias voltage of greater than about 500 V to form at least one initial trench between sidewalls of features formed in the silicon structure. The method also comprises exposing at least the sidewalls of the features to the etching chemistry at a second bias voltage of less than about 100 V to remove material from the sidewalls to expand the at least one initial trench and form at least one broader trench without substantially reducing a height of the features. Related apparatuses and electronic systems are also disclosed.

公开(公告)号：US10700073B2

公开(公告)日：2020-06-30

申请号：US16419978

申请日：2019-05-22

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Mohd Kamran Akhtar ,  Silvia Borsari ,  Alex J. Schrinsky

IPC: H01L27/108

Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.

公开(公告)号：US10347643B1

公开(公告)日：2019-07-09

申请号：US16002890

申请日：2018-06-07

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Mohd Kamran Akhtar ,  Silvia Borsari ,  Alex J. Schrinsky

IPC: H01L27/108

Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.

公开(公告)号：US20160005815A1

公开(公告)日：2016-01-07

申请号：US14853793

申请日：2015-09-14

Applicant: Micron Technology, Inc.

Inventor： Chris Larsen ,  Alex J. Schrinsky ,  John D. Hopkins ,  Matthew J. King

IPC: H01L29/06

CPC classification number: H01L29/0657 ,  H01L21/743 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0692

Abstract: Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X.

Abstract translation: 一些实施例包括具有通过至少一个虚拟突起彼此间隔开的两个台面的半导体材料的半导体结构。 虚拟突起具有沿X的横截面的宽度，并且台面具有至少3X的横截面的宽度。 一些实施例包括具有存储器阵列区域和与存储器阵列区域相邻的外围区域的半导体结构。 周边区域内的半导体材料被图案化成两个相对较宽的台面，其彼此间隔开至少一个较窄的突起。 相对窄的突起具有沿X的横截面的宽度，并且相对宽的台面具有至少3X的横截面的宽度。