公开(公告)号：US11705188B2

公开(公告)日：2023-07-18

申请号：US17529101

申请日：2021-11-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toshiaki Tsukihashi ,  Kenichi Watanabe ,  Kazuyuki Morishige ,  Moeha Shibuya ,  Kumiko Ishii

IPC: G11C11/4093 ,  H10B12/00

CPC classification number: G11C11/4093 ,  H10B12/50

Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.

公开(公告)号：US20220076736A1

公开(公告)日：2022-03-10

申请号：US17529101

申请日：2021-11-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toshiaki Tsukihashi ,  Kenichi Watanabe ,  Kazuyuki Morishige ,  Moeha Shibuya ,  Kumiko Ishii

IPC: G11C11/4093 ,  H01L27/108

Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.

公开(公告)号：US11527281B2

公开(公告)日：2022-12-13

申请号：US17218023

申请日：2021-03-30

Applicant: Micron Technology, Inc.

Inventor： Kenichi Watanabe ,  Moeha Shibuya

IPC: G11C11/4093 ,  H01L27/108

Abstract: Apparatuses with a signal line in a semiconductor device are described. An example apparatus includes one or more power supply voltage lines in a first conductive layer, a plurality of transistors and a signal line in a second conductive layer. Each transistor of the plurality of transistors includes an active region disposed in a substrate and a gate electrode above the active region. The signal line in the second conductive layer is below the first conductive layer and above the active regions of the plurality of transistors. The signal line is coupled to the gate electrodes of the plurality of transistors. The signal line has electrical resistance higher than electrical resistance of the power supply voltage line.

公开(公告)号：US11183232B2

公开(公告)日：2021-11-23

申请号：US16800899

申请日：2020-02-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toshiaki Tsukihashi ,  Kenichi Watanabe ,  Kazuyuki Morishige ,  Moeha Shibuya ,  Kumiko Ishii

IPC: G06F1/16 ,  G11C11/4093 ,  H01L27/108

Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.

公开(公告)号：US20220319580A1

公开(公告)日：2022-10-06

申请号：US17218023

申请日：2021-03-30

Applicant: Micron Technology, Inc.

Inventor： Kenichi Watanabe ,  Moeha Shibuya

IPC: G11C11/4093 ,  H01L27/108

Abstract: Apparatuses with a signal line in a semiconductor device are described. An example apparatus includes one or more power supply voltage lines in a first conductive layer, a plurality of transistors and a signal line in a second conductive layer. Each transistor of the plurality of transistors includes an active region disposed in a substrate and a gate electrode above the active region. The signal line in the second conductive layer is below the first conductive layer and above the active regions of the plurality of transistors. The signal line is coupled to the gate electrodes of the plurality of transistors. The signal line has electrical resistance higher than electrical resistance of the power supply voltage line.

公开(公告)号：US20210264967A1

公开(公告)日：2021-08-26

申请号：US16800899

申请日：2020-02-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toshiaki Tsukihashi ,  Kenichi Watanabe ,  Kazuyuki Morishige ,  Moeha Shibuya ,  Kumiko Ishii

IPC: G11C11/4093 ,  H01L27/108

Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.