公开(公告)号：US11183232B2

公开(公告)日：2021-11-23

申请号：US16800899

申请日：2020-02-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toshiaki Tsukihashi ,  Kenichi Watanabe ,  Kazuyuki Morishige ,  Moeha Shibuya ,  Kumiko Ishii

IPC: G06F1/16 ,  G11C11/4093 ,  H01L27/108

Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.

公开(公告)号：US11482274B2

公开(公告)日：2022-10-25

申请号：US17104909

申请日：2020-11-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toshiaki Tsukihashi

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/4093

Abstract: Disclosed herein is an apparatus that includes a clock generator configured to generate first, second, third, and fourth clock signals different in phase from one another, and first, second, third, and fourth clock drivers each configured to drive the first, second, third, and fourth clock signals, respectively. The first and second clock drivers are arranged symmetrically with respect to a first line extending in a first direction. The first and third clock drivers are arranged symmetrically with respect to a second line extending in a second direction. The first and fourth clock drivers are arranged symmetrically with respect to a point crossing the first and second lines.

公开(公告)号：US10854271B2

公开(公告)日：2020-12-01

申请号：US16372033

申请日：2019-04-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toshiaki Tsukihashi

IPC: G11C7/10 ,  G11C11/4076 ,  G11C11/4093

Abstract: Disclosed herein is an apparatus that includes a clock generator configured to generate first, second, third, and fourth clock signals different in phase from one another, and first, second, third, and fourth clock drivers each configured to drive the first, second, third, and fourth clock signals, respectively. The first and second clock drivers are arranged symmetrically with respect to a first line extending in a first direction. The first and third clock drivers a arranged symmetrically with respect to a second line extending in a second direction. The first and fourth clock drivers are arranged symmetrically with respect to a point crossing the first and second lines.

公开(公告)号：US20210264967A1

公开(公告)日：2021-08-26

申请号：US16800899

申请日：2020-02-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toshiaki Tsukihashi ,  Kenichi Watanabe ,  Kazuyuki Morishige ,  Moeha Shibuya ,  Kumiko Ishii

IPC: G11C11/4093 ,  H01L27/108

Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.

公开(公告)号：US20200312400A1

公开(公告)日：2020-10-01

申请号：US16372033

申请日：2019-04-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toshiaki Tsukihashi

IPC: G11C11/4076 ,  G11C11/4093

Abstract: Disclosed herein is an apparatus that includes a clock generator configured to generate first, second, third, and fourth clock signals different in phase from one another, and first, second, third, and fourth clock drivers each configured to drive the first, second, third, and fourth clock signals, respectively. The first and second clock drivers are arranged symmetrically with respect to a first line extending in a first direction. The first and third clock drivers are arranged symmetrically with respect to a second line extending in a second direction. The first and fourth clock drivers are arranged symmetrically with respect to a point crossing the first and second lines.

公开(公告)号：US11705188B2

公开(公告)日：2023-07-18

申请号：US17529101

申请日：2021-11-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toshiaki Tsukihashi ,  Kenichi Watanabe ,  Kazuyuki Morishige ,  Moeha Shibuya ,  Kumiko Ishii

IPC: G11C11/4093 ,  H10B12/00

CPC classification number: G11C11/4093 ,  H10B12/50

Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.

公开(公告)号：US20220076736A1

公开(公告)日：2022-03-10

申请号：US17529101

申请日：2021-11-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toshiaki Tsukihashi ,  Kenichi Watanabe ,  Kazuyuki Morishige ,  Moeha Shibuya ,  Kumiko Ishii

IPC: G11C11/4093 ,  H01L27/108

Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.

公开(公告)号：US20210104273A1

公开(公告)日：2021-04-08

申请号：US17104909

申请日：2020-11-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toshiaki Tsukihashi

IPC: G11C11/4076 ,  G11C11/4093

Abstract: Disclosed herein is an apparatus that includes a clock generator configured to generate first, second, third, and fourth clock signals different in phase from one another, and first, second, third, and fourth clock drivers each configured to drive the first, second, third, and fourth clock signals, respectively. The first and second clock drivers are arranged symmetrically with respect to a first line extending in a first direction. The first and third clock drivers are arranged symmetrically with respect to a second line extending in a second direction. The first and fourth clock drivers are arranged symmetrically with respect to a point crossing the first and second lines.