公开(公告)号：US20210005227A1

公开(公告)日：2021-01-07

申请号：US17028558

申请日：2020-09-22

Applicant: Micron Technology, Inc.

Inventor： Kazuhiro Yoshida ,  Kumiko Ishii

IPC: G11C5/02 ,  G11C8/18 ,  G11C7/22 ,  G11C5/04 ,  G11C7/10 ,  G11C5/06

Abstract: Memory devices, memory systems, and systems, include memory devices with a bonding pad region including two or more bonding pads for operably coupling to external signals and a number of command-and-address (CA) input signals. The memory device also includes centralized CA interface region including two or more CA input circuits operably coupled to the number of input signals. One of the tow or more CA input circuits for each CA input signal may border at least two other CA input circuits coupled to different CA input signals.

公开(公告)号：US10811057B1

公开(公告)日：2020-10-20

申请号：US16365168

申请日：2019-03-26

Applicant: Micron Technology, Inc.

Inventor： Kazuhiro Yoshida ,  Kumiko Ishii

IPC: G11C5/02 ,  G11C8/18 ,  G11C7/22 ,  G11C5/04 ,  G11C7/10 ,  G11C5/06

Abstract: Memory devices, memory systems, and systems, include memory devices with a bonding pad region including two or more bonding pads for operably coupling to external signals and two or more command-and-address (CA) input signals. The memory device also includes a memory cell region for storing information in a plurality of memory cells. A centralized CA interface region including two or more CA input circuits operably coupled to the two or more CA input signals. The centralized CA interface region is positioned between the bonding pad region and the memory cell region in a layout arrangement with the two or more CA input circuits neighboring each other in a compact region such that clock routing to the two or more CA input circuits is substantially reduced.

公开(公告)号：US11727962B2

公开(公告)日：2023-08-15

申请号：US17448278

申请日：2021-09-21

Applicant: Micron Technology, Inc.

Inventor： Kazuhiro Yoshida ,  Kumiko Ishii

IPC: G11C5/02 ,  G11C8/18 ,  G11C7/22 ,  G11C5/04 ,  G11C7/10 ,  G11C5/06

CPC classification number: G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C7/109 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/225 ,  G11C8/18

Abstract: Devices are disclosed. A device may include an interface region including two or more input circuits operably coupled to the number of input signals, wherein one of the two or more input circuits for each input signal is adjacent at least two other input circuits coupled to different input. Associated systems are also disclosed.

公开(公告)号：US20220005510A1

公开(公告)日：2022-01-06

申请号：US17448278

申请日：2021-09-21

Applicant: Micron Technology, Inc.

Inventor： Kazuhiro Yoshida ,  Kumiko Ishii

IPC: G11C5/02 ,  G11C8/18 ,  G11C7/22 ,  G11C5/04 ,  G11C7/10 ,  G11C5/06

Abstract: Devices are disclosed. A device may include an interface region including two or more input circuits operably coupled to the number of input signals, wherein one of the two or more input circuits for each input signal is adjacent at least two other input circuits coupled to different input. Associated systems are also disclosed.

公开(公告)号：US20200312378A1

公开(公告)日：2020-10-01

申请号：US16365168

申请日：2019-03-26

Applicant: Micron Technology, Inc.

Inventor： Kazuhiro Yoshida ,  Kumiko Ishii

IPC: G11C5/02 ,  G11C8/18 ,  G11C7/22 ,  G11C7/10 ,  G11C5/06 ,  G11C5/04

Abstract: Memory devices, memory systems, and systems, include memory devices with a bonding pad region including two or more bonding pads for operably coupling to external signals and two or more command-and-address (CA) input signals. The memory device also includes a memory cell region for storing information in a plurality of memory cells. A centralized CA interface region including two or more CA input circuits operably coupled to the two or more CA input signals. The centralized CA interface region is positioned between the bonding pad region and the memory cell region in a layout arrangement with the two or more CA input circuits neighboring each other in a compact region such that clock routing to the two or more CA input circuits is substantially reduced.

公开(公告)号：US11183232B2

公开(公告)日：2021-11-23

申请号：US16800899

申请日：2020-02-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toshiaki Tsukihashi ,  Kenichi Watanabe ,  Kazuyuki Morishige ,  Moeha Shibuya ,  Kumiko Ishii

IPC: G06F1/16 ,  G11C11/4093 ,  H01L27/108

Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.

公开(公告)号：US11705188B2

公开(公告)日：2023-07-18

申请号：US17529101

申请日：2021-11-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toshiaki Tsukihashi ,  Kenichi Watanabe ,  Kazuyuki Morishige ,  Moeha Shibuya ,  Kumiko Ishii

IPC: G11C11/4093 ,  H10B12/00

CPC classification number: G11C11/4093 ,  H10B12/50

Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.

公开(公告)号：US20220076736A1

公开(公告)日：2022-03-10

申请号：US17529101

申请日：2021-11-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toshiaki Tsukihashi ,  Kenichi Watanabe ,  Kazuyuki Morishige ,  Moeha Shibuya ,  Kumiko Ishii

IPC: G11C11/4093 ,  H01L27/108

Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.

公开(公告)号：US11164608B2

公开(公告)日：2021-11-02

申请号：US17028558

申请日：2020-09-22

Applicant: Micron Technology, Inc.

Inventor： Kazuhiro Yoshida ,  Kumiko Ishii

IPC: G11C5/02 ,  G11C8/18 ,  G11C7/22 ,  G11C5/04 ,  G11C7/10 ,  G11C5/06

Abstract: Memory devices, memory systems, and systems, include memory devices with a bonding pad region including two or more bonding pads for operably coupling to external signals and a number of command-and-address (CA) input signals. The memory device also includes a centralized CA interface region including two or more CA input circuits operably coupled to the number of input signals. One of the two or more CA input circuits for each CA input signal may border at least two other CA input circuits coupled to different CA input signals.

公开(公告)号：US20210264967A1

公开(公告)日：2021-08-26

申请号：US16800899

申请日：2020-02-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toshiaki Tsukihashi ,  Kenichi Watanabe ,  Kazuyuki Morishige ,  Moeha Shibuya ,  Kumiko Ishii

IPC: G11C11/4093 ,  H01L27/108

Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.