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公开(公告)号：US20230403184A1
公开(公告)日：2023-12-14
申请号：US18214876
申请日：2023-06-27
Applicant: Micron Technology, Inc.
Inventor： Jennifer E. Taylor , Raghukiran Sreeramaneni
CPC classification number: H04L25/03267 , H04L25/03949 , H04L25/06 , H04L25/062 , H04L25/03057
Abstract: A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.
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公开(公告)号：US20210158851A1
公开(公告)日：2021-05-27
申请号：US17170616
申请日：2021-02-08
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sujeet Ayyapureddi , Raghukiran Sreeramaneni
IPC: G11C11/408 , G11C11/406 , G11C11/16 , G11C11/4074 , G11C15/04
Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for analog row access rate determination. Accesses to different row addresses may be tracked by storing one or more received addresses in a slice of stack. Each slice includes an accumulator circuit which provides a voltage based on charge on a capacitor. When a row address is received, it may be compared to the row addresses stored in the stack, and if there is a match, the charge on the capacitor in the associated accumulator circuit is increased. Each slice may also include a voltage to time (VtoT) circuit which may be used to identify the highest of the voltages provided by the accumulator circuits. The row address stored in the slide with the highest voltage may be refreshed.
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公开(公告)号：US20210057012A1
公开(公告)日：2021-02-25
申请号：US16548027
申请日：2019-08-22
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sujeet Ayyapureddi , Raghukiran Sreeramaneni
IPC: G11C11/408 , G11C11/406 , G11C11/4074 , G11C11/16 , G11C15/04
Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for analog row access rate determination. Accesses to different row addresses may be tracked by storing one or more received addresses in a slice of stack. Each slice includes an accumulator circuit which provides a voltage based on charge on a capacitor. When a row address is received, it may be compared to the row addresses stored in the stack, and if there is a match, the charge on the capacitor in the associated accumulator circuit is increased. Each slice may also include a voltage to time (VtoT) circuit which may be used to identify the highest of the voltages provided by the accumulator circuits. The row address stored in the slide with the highest voltage may be refreshed.
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公开(公告)号：US20200280467A1
公开(公告)日：2020-09-03
申请号：US16878288
申请日：2020-05-19
Applicant: Micron Technology, Inc.
Inventor： Jennifer E. Taylor , Raghukiran Sreeramaneni
Abstract: A device including an equalizer that includes a first input configured to receive an input signal, a second input configured to receive a reference signal, and a third input configured to receive an adjustment signal. The equalizer also includes a first output configured to transmit a corrected signal, wherein the corrected signal is generated based on data outputs controlled via the input signal, the reference signal, and a clock signal, wherein the data outputs are modified based on the first adjustment signal, wherein corrected signal offsets inter-symbol interference on the input signal based on a data bit received at the first input prior to reception of the input signal.
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公开(公告)号：US10666470B2
公开(公告)日：2020-05-26
申请号：US16289517
申请日：2019-02-28
Applicant: Micron Technology, Inc.
Inventor： Jennifer E. Taylor , Raghukiran Sreeramaneni
IPC: H04L25/03 , G11C11/401 , G11C7/10
Abstract: A device including an equalizer that includes a first input configured to receive an input signal, a second input configured to receive a reference signal, and a third input configured to receive an adjustment signal. The equalizer also includes a first output configured to transmit a corrected signal, wherein the corrected signal is generated based on data outputs controlled via the input signal, the reference signal, and a clock signal, wherein the data outputs are modified based on the first adjustment signal, wherein corrected signal offsets inter-symbol interference on the input signal based on a data bit received at the first input prior to reception of the input signal.
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Patent Agency Ranking
公开(公告)号：US10529391B2
公开(公告)日：2020-01-07
申请号：US16517165
申请日：2019-07-19
Applicant: Micron Technology, Inc.
Inventor： Raghukiran Sreeramaneni , Jennifer E. Taylor
Abstract: A device includes a signal input to receive a data input as part of a bit stream. The device also includes a reference input to receive a reference signal. The device further includes push circuitry to receive a first weight value, receive a first correction value, and generate a push signal based on the first weight value and the first correction value to selectively modify the data input as well as pull circuitry to receive a second weight value, receive a second correction value, and generate a pull signal based on the second weight value and the second correction value to selectively modify the data input.
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公开(公告)号：US10373659B2
公开(公告)日：2019-08-06
申请号：US15850965
申请日：2017-12-21
Applicant: Micron Technology, Inc.
Inventor： Raghukiran Sreeramaneni , Jennifer E. Taylor
Abstract: A device includes a signal input to receive a data input as part of a bit stream. The device also includes a reference input to receive a reference signal. The device further includes push circuitry to receive a first weight value, receive a first correction value, and generate a push signal based on the first weight value and the first correction value to selectively modify the data input as well as pull circuitry to receive a second weight value, receive a second correction value, and generate a pull signal based on the second weight value and the second correction value to selectively modify the data input.
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公开(公告)号：US20190147968A1
公开(公告)日：2019-05-16
申请号：US16216948
申请日：2018-12-11
Applicant: Micron Technology, Inc.
Inventor： Raghukiran Sreeramaneni , William J. Wilcox , Girish N. Cherussery
Abstract: A method of operating an electronic device includes: precharging a fuse read node to an intermediate voltage less than an input voltage, wherein the fuse read node connects a fuse array and a fuse read circuit, the fuse array including a fuse cell configured to store information and the fuse read circuit configured to read the stored information; connecting the fuse cell to the fuse read node for reading the information; and determining, with the fuse read circuit, the information from the fuse cell based on changes to the intermediate voltage at the fuse read node.
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公开(公告)号：US20190097848A1
公开(公告)日：2019-03-28
申请号：US15716162
申请日：2017-09-26
Applicant: Micron Technology, Inc.
Inventor： Jennifer E. Taylor , Raghukiran Sreeramaneni
Abstract: A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.
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公开(公告)号：US10147466B1
公开(公告)日：2018-12-04
申请号：US15716132
申请日：2017-09-26
Applicant: Micron Technology, Inc.
Inventor： Jennifer E. Taylor , Raghukiran Sreeramaneni
Abstract: A device includes a combinational circuit configured to create a one or more distortion correction factors used offset inter-symbol interference from a data stream on a distorted bit. The device also includes a selection circuit coupled o the combinational circuit. The selection circuit includes a feedback pin configured to receive a control signal and an output, wherein the selection circuit is configured to select a first distortion correction factor of the one or more distortion correction factors based upon the control signal and transmit the first distortion correction factor from the output.
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