公开(公告)号：US20180197595A1

公开(公告)日：2018-07-12

申请号：US15719349

申请日：2017-09-28

Applicant: Micron Technology, Inc.

Inventor： Shunichi Saito ,  Toshio Sugano ,  Atsushi Hiraishi ,  Atsuo Koshizuka

IPC: G11C11/4093 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/4097

CPC classification number: G11C11/4093 ,  G11C7/1012 ,  G11C7/1075 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/107

Abstract: Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O line pair. A second I/O line pair may be provided coupled to a second local I/O line pair. The apparatus may further include a first bit line including at least a first memory cell and a second memory cell, and a second bit line including at least a third memory cell and a fourth memory cell may be provided. The first local I/O line pair may be coupled to at least one of the first and second bit lines, and the second local I/O line pair is coupled to at least one of the first and second bit lines.

公开(公告)号：US10049722B2

公开(公告)日：2018-08-14

申请号：US15719349

申请日：2017-09-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shunichi Saito ,  Toshio Sugano ,  Atsushi Hiraishi ,  Atsuo Koshizuka

IPC: G11C5/06 ,  G11C11/4093 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/4074 ,  G11C11/4097 ,  G11C11/4096 ,  G11C11/4091

CPC classification number: G11C11/4093 ,  G11C7/1012 ,  G11C7/1075 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/107

Abstract: Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O line pair. A second I/O line pair may be provided coupled to a second local I/O line pair. The apparatus may further include a first bit line including at least a first memory cell and a second memory cell, and a second bit line including at least a third memory cell and a fourth memory cell may be provided. The first local I/O line pair may be coupled to at least one of the first and second bit lines, and the second local I/O line pair is coupled to at least one of the first and second bit lines.

公开(公告)号：US09805786B1

公开(公告)日：2017-10-31

申请号：US15400653

申请日：2017-01-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shunichi Saito ,  Toshio Sugano ,  Atsushi Hiraishi ,  Atsuo Koshizuka

IPC: G11C5/06 ,  G11C11/4093 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/4093 ,  G11C7/1012 ,  G11C7/1075 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/107

Abstract: Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O line pair. A second I/O line pair may be provided coupled to a second local I/O line pair. The apparatus may further include a first bit line including at least a first memory cell and a second memory cell, and a second bit line including at least a third memory cell and a fourth memory cell may be provided. The first local I/O line pair may be coupled to at least one of the first and second bit lines, and the second local I/O line pair is coupled to at least one of the first and second bit lines.

公开(公告)号：US20160267962A1

公开(公告)日：2016-09-15

申请号：US15159001

申请日：2016-05-19

Applicant: Micron Technology, Inc.

Inventor： Shunichi Saito ,  Toshio Sugano ,  Atsushi Hiraishi

IPC: G11C11/406

CPC classification number: G11C11/40615 ,  G11C11/40603 ,  G11C16/26

Abstract: A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.

公开(公告)号：US09837137B2

公开(公告)日：2017-12-05

申请号：US15159001

申请日：2016-05-19

Applicant: Micron Technology, Inc.

Inventor： Shunichi Saito ,  Toshio Sugano ,  Atsushi Hiraishi

IPC: G11C16/26 ,  G11C11/406

CPC classification number: G11C11/40615 ,  G11C11/40603 ,  G11C16/26

Abstract: A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.