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    TIMING SIGNAL DELAY COMPENSATION IN A MEMORY DEVICE
    1.
    发明申请
    TIMING SIGNAL DELAY COMPENSATION IN A MEMORY DEVICE 有权

    公开(公告)号：US20210319816A1

    公开(公告)日：2021-10-14

    申请号：US16843628

    申请日：2020-04-08

    Applicant: Micron Technology, Inc.

    Inventor： Zhi Qi Huang ,  Wei Lu Chu ,  Dong Pan

    IPC: G11C7/22 ,  G11C7/04 ,  G11C7/10

    Abstract: Methods, systems, and devices for timing signal delay compensation in a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. In accordance with examples as disclosed herein, a memory device may include delay components having a variable and configurable impedance, where the configurable impedance may be based at least in part on a configuration signal generated at the memory device. A configuration signal may be generated based on fabrication characteristics of the memory device, or based on operating conditions of the memory device, or various combinations thereof.

    AMPLIFIER INPUT PAIR PROTECTION
    3.
    发明申请
    AMPLIFIER INPUT PAIR PROTECTION 有权

    公开(公告)号：US20230044187A1

    公开(公告)日：2023-02-09

    申请号：US17393597

    申请日：2021-08-04

    Applicant: Micron Technology, Inc.

    Inventor： Zhi Qi Huang ,  Wei Lu Chu

    IPC: G11C11/4074 ,  H03F3/45 ,  G05F3/26

    Abstract: A memory device includes a voltage generator configured to generate a reference voltage for transmission to at least one component of the memory device. The voltage generator includes a first input to receive a first signal having a first voltage value. The voltage generator also includes a second input to receive a second signal having a second voltage value. The voltage generator further includes a first circuit configured to generate third voltage and a second circuit coupled to the first circuit to receive the third voltage value, wherein the second circuit receives the first signal and the second signal and is configured to utilize the third voltage value to facilitate comparison of the first voltage value and the second voltage value to generate an output voltage.

    Apparatuses and methods for voltage dependent delay
    4.
    发明授权
    Apparatuses and methods for voltage dependent delay 有权

    公开(公告)号：US10897244B1

    公开(公告)日：2021-01-19

    申请号：US16545384

    申请日：2019-08-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Zhi Qi Huang ,  Wei Lu Chu ,  Dong Pan

    IPC: G11C7/00 ,  H03K5/131 ,  H03K5/134 ,  G11C8/18 ,  G11C5/14 ,  H03K5/00

    Abstract: Apparatus and methods are described for voltage dependent delay. An example apparatus includes an oscillator including a delay circuit that is configured to provide an oscillating output signal has a delay based on a delay of the delay circuit. The delay of the delay circuit is based on a voltage it receives. For example, the delay of the delay circuit increases for an increasing received voltage and decreases for a decreasing received voltage. As a result, the oscillating output signal provided by the oscillator is based on the received voltage. For example, a frequency of the oscillating output signal decreases for increasing received voltage and increases for decreasing received voltage. Described in another way, the frequency of the oscillating output signal is relatively low for relatively high received voltage and relatively high for relatively low received voltage.

    TIMING CIRCUIT HAVING TUNED TEMPERATURE DEPENDENCY
    6.
    发明公开
    TIMING CIRCUIT HAVING TUNED TEMPERATURE DEPENDENCY 审中-公开

    公开(公告)号：US20230178139A1

    公开(公告)日：2023-06-08

    申请号：US17922199

    申请日：2020-05-29

    Applicant: Micron Technology, Inc.

    Inventor： Si Hong Kim ,  Ki-Jun Nam ,  Zhi Qi Huang ,  John David Porter

    IPC: G11C11/4076

    CPC classification number: G11C11/4076

    Abstract: A system (100) for providing a timing signal with tunable temperature dependency in an electronic device may include a timing circuit (102) and an initial setting circuit (104). The timing circuit (102) may include a delay stage (106) and a gate stage (108). The delay stage (106) may be configured to receive an input signal and to produce a delayed signal by introducing a delay to the input signal. The gate stage (108) may be configured to receive the delayed signal and a threshold setting signal, to produce an output signal using the delayed signal and a logic threshold, and to set an initial value of the logic threshold according to the threshold setting signal. The initial setting circuit (104) may be configured to allow the threshold setting signal to be tuned for providing the time delay with a specified temperature dependency.

    AMPLIFIER WITH A CONTROLLABLE PULL-DOWN CAPABILITY FOR A MEMORY DEVICE
    7.
    发明申请
    AMPLIFIER WITH A CONTROLLABLE PULL-DOWN CAPABILITY FOR A MEMORY DEVICE 有权

    公开(公告)号：US20220200538A1

    公开(公告)日：2022-06-23

    申请号：US17127172

    申请日：2020-12-18

    Applicant: Micron Technology, Inc.

    Inventor： Wei Lu Chu ,  Zhi Qi Huang ,  Dong Pan

    IPC: H03F1/30 ,  H03F1/02 ,  G11C7/06

    Abstract: Methods, systems, and devices for operating an amplifier with a controllable pull-down capability are described. A memory device may include a memory array and a power circuit that generates an internal signal for components in the memory array. The power circuit may include an amplifier and a power transistor that is coupled with the amplifier. A pull-down capability of the amplifier may be controllable using an external signal that is based on a difference between a reference signal and the internal signal. The power circuit may also include a comparator that is coupled with the amplifier and configured to compare the reference signal and the internal signal. Components of the comparator may be integrated with components of the amplifier, may share a bias circuit, and may use nodes within the amplifier to control the comparator. A signal output by the comparator may control the pull-down capability of the amplifier.

    Amplifier with a controllable pull-down capability for a memory device
    9.
    发明授权
    Amplifier with a controllable pull-down capability for a memory device 有权

    公开(公告)号：US11632084B2

    公开(公告)日：2023-04-18

    申请号：US17127172

    申请日：2020-12-18

    Applicant: Micron Technology, Inc.

    Inventor： Wei Lu Chu ,  Zhi Qi Huang ,  Dong Pan

    IPC: H03F3/45 ,  H03F1/30 ,  G11C7/06 ,  H03F1/02

    Abstract: Methods, systems, and devices for operating an amplifier with a controllable pull-down capability are described. A memory device may include a memory array and a power circuit that generates an internal signal for components in the memory array. The power circuit may include an amplifier and a power transistor that is coupled with the amplifier. A pull-down capability of the amplifier may be controllable using an external signal that is based on a difference between a reference signal and the internal signal. The power circuit may also include a comparator that is coupled with the amplifier and configured to compare the reference signal and the internal signal. Components of the comparator may be integrated with components of the amplifier, may share a bias circuit, and may use nodes within the amplifier to control the comparator. A signal output by the comparator may control the pull-down capability of the amplifier.

    Timing signal delay compensation in a memory device
    10.
    发明授权
    Timing signal delay compensation in a memory device 有权

    公开(公告)号：US11587602B2

    公开(公告)日：2023-02-21

    申请号：US17526846

    申请日：2021-11-15

    Applicant: Micron Technology, Inc.

    Inventor： Zhi Qi Huang ,  Wei Lu Chu ,  Dong Pan

    IPC: G11C7/22 ,  G11C7/04 ,  G11C7/10

    Abstract: Methods, systems, and devices for timing signal delay compensation in a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. In accordance with examples as disclosed herein, a memory device may include delay components having a variable and configurable impedance, where the configurable impedance may be based at least in part on a configuration signal generated at the memory device. A configuration signal may be generated based on fabrication characteristics of the memory device, or based on operating conditions of the memory device, or various combinations thereof.

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