公开(公告)号：US6433586B2

公开(公告)日：2002-08-13

申请号：US35635199

申请日：1999-07-19

申请人： MITSUBISHI ELECTRIC CORP

发明人： OOISHI TSUKASA

IPC分类号： H03K3/356 ,  G11C11/407 ,  H03K3/012 ,  H03K3/3562 ,  H03K19/00

CPC分类号： H03K19/0016 ,  H03K3/012 ,  H03K3/35625

摘要： A logical processing part is formed by a pass transistor logic element, and an output signal of the pass transistor logic element is applied to the gates of MOS transistors for differentially amplifying and latching the output signal in the latch stage. This latch stage is formed by master and slave latch circuits, and power supply to the master latch circuit is cut off while holding an information signal only in the slave latch circuit with the level of a power supply voltage thereto increased, reducing a leakage current in a sleep mode or a power down mode. A logic circuit correctly operating at a high speed with low current consumption under a low power supply voltage is provided.

摘要翻译： 逻辑处理部分由传输晶体管逻辑元件形成，并且传输晶体管逻辑元件的输出信号被施加到MOS晶体管的栅极，用于在锁存级中差分放大和锁存输出信号。 该锁存级由主锁存电路和从锁存电路形成，并且只有在从锁存电路中保持信息信号而使主锁存电路的电源被切断，同时电源电压的电平增加，减少了泄漏电流 休眠模式或掉电模式。 提供了在低电源电压下以低速电流正确工作的逻辑电路。

公开(公告)号：US6434075B2

公开(公告)日：2002-08-13

申请号：US52574900

申请日：2000-03-14

申请人： MITSUBISHI ELECTRIC CORP

发明人： OOISHI TSUKASA

IPC分类号： G11C11/403 ,  G11C7/06 ,  G11C7/10 ,  G11C11/401 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4091 ,  G11C7/00

CPC分类号： G11C7/06 ,  G11C7/1045 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4074 ,  G11C11/4091

摘要： In a DRAM employing a shared sense amplifier method, a bit line select signal falls to the level of ground potential after a potential difference is generated between a pair of bit lines and sense nodes in response to activation of a word line in a self refresh mode for disconnecting the bit line pair in a memory block including the activated word line from a sense amplifier. When the potentials of the sense nodes are amplified by the sense amplifier, the disconnected bit line pair is connected again to the sense amplifier.

摘要翻译： 在采用共享读出放大器方法的DRAM中，响应于自刷新模式中的字线的激活，在一对位线和感测节点之间产生电位差之后，位线选择信号下降到地电位水平 用于在包括来自读出放大器的激活字线的存储器块中断开位线对。 当感测放大器放大感测节点的电位时，断开的位线对再次连接到读出放大器。

公开(公告)号：US6373315B2

公开(公告)日：2002-04-16

申请号：US79399701

申请日：2001-02-28

申请人： MITSUBISHI ELECTRIC CORP

发明人： TSUJI TAKAHARU ,  TOMISHIMA SHIGEKI ,  OOISHI TSUKASA

IPC分类号： H03K19/017 ,  H03K19/0185 ,  H03L5/00

CPC分类号： H03K19/01721 ,  H03K19/018521

摘要： In a signal potential conversion circuit of a DRAM, a first P channel MOS transistor for charging a first node is connected in parallel with a second P channel MOS transistor and the second P channel MOS transistor is turned on in a pulse manner in response to a rising edge of an input signal. Further, the first P channel MOS transistor has its current drive ability defined to be approximately one-tenth of that of an N channel MOS transistor for discharging the first node. Accordingly, each of the first node and a second node can be charged and discharged quickly to enable conversion of a signal potential to be accomplished speedily.

摘要翻译： 在DRAM的信号电位转换电路中，用于对第一节点充电的第一P沟道MOS晶体管与第二P沟道MOS晶体管并联连接，并且第二P沟道MOS晶体管以脉冲方式响应于 输入信号的上升沿。 此外，第一P沟道MOS晶体管的电流驱动能力被定义为用于放电第一节点的N沟道MOS晶体管的大约十分之一。 因此，可以快速地对第一节点和第二节点中的每一个进行充电和放电，以便能够快速地实现信号电位的转换。