Abstract:
A semiconductor memory device, including: a memory cell connected to a first bitline and associated with a second bitline; a sense amplifier, including a first input/output node and a second input/output node; and an isolator connected to the bitlines and to the input/output nodes, the isolator being configured to carry out bitline isolation during a refresh operation of the memory cell, where the bitline isolation includes electrically disconnecting the first bitline from the first input/output node and electrically disconnecting the second bitline from the second input/output node, followed by: electrically re-connecting the first bitline to the first input/output node while the second bitline remains electrically disconnected from the second input/output node.
Abstract:
A plurality of devices are operated by storing at a device a first ID number received at a first port of the device and a second ID number received at a second port of the device. The device receives a data command through at least one of the first and second ports. The data command has a command ID number. The device executes the data command when at least one of the command ID number is equal to the first ID number when the data command is received at the first port and the command ID number is equal to the second ID number when the data command is received at the second port.
Abstract:
A method and apparatus for organizing memory for a computer system including a plurality of memory devices 2, 3, connected to a logic device 1, particularly a memory system having a plurality of stacked memory dice connected to a logic die, with the logic device 1 having capability to analyze and compensate for differing delays to the stacked devices 2,3,4,5 stacking multiple dice divided into partitions serviced by multiple buses 21,22 connected to a logic die 1, to increase throughput between the devices 2,3 and logic 1 device allowing large scale integration of memory with self-healing capability.