SEMICONDUCTOR MEMORY DEVICE WITH SENSE AMPLIFIER AND BITLINE ISOLATION
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE WITH SENSE AMPLIFIER AND BITLINE ISOLATION 有权
    具有检测放大器和位线隔离的半导体存储器件

    公开(公告)号:US20130265839A1

    公开(公告)日:2013-10-10

    申请号:US13912650

    申请日:2013-06-07

    Inventor: Byoung Jin CHOI

    Abstract: A semiconductor memory device, including: a memory cell connected to a first bitline and associated with a second bitline; a sense amplifier, including a first input/output node and a second input/output node; and an isolator connected to the bitlines and to the input/output nodes, the isolator being configured to carry out bitline isolation during a refresh operation of the memory cell, where the bitline isolation includes electrically disconnecting the first bitline from the first input/output node and electrically disconnecting the second bitline from the second input/output node, followed by: electrically re-connecting the first bitline to the first input/output node while the second bitline remains electrically disconnected from the second input/output node.

    Abstract translation: 一种半导体存储器件,包括:连接到第一位线并与第二位线相关联的存储器单元; 读出放大器,包括第一输入/输出节点和第二输入/输出节点; 以及连接到所述位线和所述输入/输出节点的隔离器,所述隔离器被配置为在所述存储器单元的刷新操作期间执行位线隔离,其中所述位线隔离包括将所述第一位线与所述第一输入/输出节点电断开 并且将所述第二位线与所述第二输入/输出节点电断开,其后是:将所述第一位线电连接到所述第一输入/输出节点,同时所述第二位线与所述第二输入/输出节点电连接断开。

    HIGH SPEED INTERFACE FOR DAISY-CHAINED DEVICES
    2.
    发明申请
    HIGH SPEED INTERFACE FOR DAISY-CHAINED DEVICES 审中-公开
    用于家庭装置的高速接口

    公开(公告)号:US20130275628A1

    公开(公告)日:2013-10-17

    申请号:US13914126

    申请日:2013-06-10

    Inventor: Byoung Jin CHOI

    CPC classification number: G06F3/061 G06F13/4234 G06F13/4243 G06F13/4256

    Abstract: A plurality of devices are operated by storing at a device a first ID number received at a first port of the device and a second ID number received at a second port of the device. The device receives a data command through at least one of the first and second ports. The data command has a command ID number. The device executes the data command when at least one of the command ID number is equal to the first ID number when the data command is received at the first port and the command ID number is equal to the second ID number when the data command is received at the second port.

    Abstract translation: 通过在设备处存储在设备的第一端口处接收到的第一ID号码和在设备的第二端口处接收到的第二ID号码来操作多个设备。 设备通过第一和第二端口中的至少一个接收数据命令。 data命令有一个命令ID号。 当在第一端口接收到数据命令时,当至少一个命令ID号码等于第一ID号码并且当接收到数据命令时命令ID号码等于第二ID号码时,设备执行数据命令 在第二个港口

    MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE
    3.
    发明申请
    MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE 有权
    使用堆积存储器设备的存储器系统和方法

    公开(公告)号:US20130135917A1

    公开(公告)日:2013-05-30

    申请号:US13684260

    申请日:2012-11-23

    Inventor: Byoung Jin CHOI

    Abstract: A method and apparatus for organizing memory for a computer system including a plurality of memory devices 2, 3, connected to a logic device 1, particularly a memory system having a plurality of stacked memory dice connected to a logic die, with the logic device 1 having capability to analyze and compensate for differing delays to the stacked devices 2,3,4,5 stacking multiple dice divided into partitions serviced by multiple buses 21,22 connected to a logic die 1, to increase throughput between the devices 2,3 and logic 1 device allowing large scale integration of memory with self-healing capability.

    Abstract translation: 一种用于组织包括连接到逻辑设备1的多个存储器件2,3的计算机系统的存储器的方法和装置,特别是具有连接到逻辑管芯的多个堆叠的存储器管芯的存储器系统与逻辑器件1 具有分析和补偿堆叠设备2,3,4,5的不同延迟的能力,2,3,4,5将多个骰子分成多个分割成连接到逻辑管芯1的多个总线21,22所服务的分区,以增加器件2,3和 逻辑1器件允许大规模集成存储器与自我修复能力。

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