公开(公告)号：US20030034503A1

公开(公告)日：2003-02-20

申请号：US09930176

申请日：2001-08-16

Applicant: MOTOROLA, INC.

Inventor： Raymond B. Essick IV ,  David P. Gurney ,  Timothy J. Johnson ,  Dale F. Bengtson

IPC: H01L029/04

CPC classification number: G06F9/38 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8258 ,  H01L27/0605

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. These materials and techniques can be advantageously utilized to fabricate a processing device having instruction decoders and instruction dispatchers.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。 可以有利地利用这些材料和技术来制造具有指令解码器和指令调度器的处理装置。

公开(公告)号：US20030034502A1

公开(公告)日：2003-02-20

申请号：US09930259

申请日：2001-08-16

Applicant: MOTOROLA, INC.

Inventor： Mihir A. Pandya ,  Raymond B. Essick IV ,  David P. Gurney

IPC: H01L029/74

CPC classification number: H01L21/8258 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L27/0605

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. Furthermore, a pre-computation unit is implemented in the compound semiconductor material to pre-compute instructions directly in the memory system, thereby resulting in substantially increased processing throughput.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。 此外，在化合物半导体材料中实现预计算单元以直接在存储器系统中计算指令，从而导致大大增加的处理吞吐量。

公开(公告)号：US20030036259A1

公开(公告)日：2003-02-20

申请号：US09930275

申请日：2001-08-16

Applicant: MOTOROLA, INC.

Inventor： Larry R. Tate ,  David P. Gurney

IPC: G06F015/00 ,  H01L021/00 ,  H01L021/8238

CPC classification number: H01L27/0605 ,  H01L21/8258

Abstract: A method and apparatus for bus compression in an array processing system, involving providing a data bus making multiple data bus connections between two separate processing modules; compressing bus signals outputted by at least one of the processing modules with an associated bus modulator effective to permit concurrent transfer of a plurality of bits of information per connection; transferring the compressed signals via the data bus to a bus demodulator associated with the other processing module, wherein the demodulator reconstructs the bus signals before inputting the signals to the other processing module; wherein at least one of the processing modules is formed at least in part in CMOS in a unique semiconductor structure.

Abstract translation: 一种在阵列处理系统中用于总线压缩的方法和装置，包括提供在两个单独的处理模块之间进行多个数据总线连接的数据总线; 利用相关联的总线调制器压缩由至少一个处理模块输出的总线信号，该总线调制器有效地允许每个连接同时传送多个位信息; 将经由数据总线的压缩信号传送到与另一个处理模块相关联的总线解调器，其中解调器在将信号输入到另一个处理模块之前重构总线信号; 其中所述处理模块中的至少一个至少部分地以独特的半导体结构形成在CMOS中。

公开(公告)号：US20030014457A1

公开(公告)日：2003-01-16

申请号：US09905441

申请日：2001-07-13

Applicant: MOTOROLA, INC.

Inventor： Vipul A. Desai ,  David P. Gurney ,  Benson Chau

IPC: G06F007/32

CPC classification number: G06F7/57 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3885 ,  G06F15/8076 ,  G06F2207/3828

Abstract: A processor includes a first vector processing unit including a first register file and first vector arithmetic logic unit; a second vector processing unit including a second register file and second vector arithmetic logic unit wherein the first register file has a first plurality of cross connections to the second vector arithmetic logic unit; wherein the second register file as a second plurality of cross connections to the first vector arithmetic logic unit.

Abstract translation: 处理器包括：第一矢量处理单元，包括第一寄存器堆和第一矢量运算逻辑单元; 第二矢量处理单元，包括第二寄存器堆和第二矢量运算逻辑单元，其中第一寄存器堆具有与第二矢量运算逻辑单元的第一多个交叉连接; 其中所述第二寄存器堆作为与所述第一向量运算逻辑单元的第二多个交叉连接。