公开(公告)号：US20030016567A1

公开(公告)日：2003-01-23

申请号：US09909905

申请日：2001-07-23

Applicant: MOTOROLA, INC.

Inventor： Peter J. Wilson ,  Mihir A. Pandya

IPC: H01L029/04

CPC classification number: G11C7/1006 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8258 ,  H01L27/0605 ,  H01S5/026 ,  H01S5/0261 ,  H01S5/183 ,  H01S5/423 ,  H01S2301/176

Abstract: An apparatus includes a memory system having multiple memory subsystems that are operable to concurrently service memory transactions. The memory system has an interface arrangement with an interconnection network that allows for independent access to each memory subsystem, and logic blocks that support the servicing and distribution or routing of memory transactions. Preferably, the apparatus is formed on a semiconductor structure having a combination of compound semiconductor material and Group IV semiconductor material.

Abstract translation: 一种装置包括具有可操作以同时服务存储器事务的多个存储器子系统的存储器系统。 存储器系统具有与互连网络的接口布置，其允许对每个存储器子系统的独立访问，以及支持存储器事务的服务和分发或路由的逻辑块。 优选地，该装置形成在具有化合物半导体材料和IV族半导体材料的组合的半导体结构上。

公开(公告)号：US20030034541A1

公开(公告)日：2003-02-20

申请号：US09930270

申请日：2001-08-16

Applicant: MOTOROLA, INC.

Inventor： Raymond B. Essick ,  Mihir A. Pandya

IPC: H01L029/00 ,  H01L029/167 ,  H01L029/207 ,  H01L029/227 ,  H01L023/58 ,  H01L031/0288

CPC classification number: H01L27/0605 ,  H01L21/02192 ,  H01L21/02197 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/31691 ,  H01L21/8258

Abstract: Fault remediation functions are embodied in a semiconductor structure in which high quality epitaxial layers of monocrystalline materials are made to overlie monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Fault remediation is carried out in one instance by recognizing the presence of a fault and in another instance by providing fault correction. The fault remediation functions may be combined with conventional data-emitting circuitry to form a monolithic structure having a common substrate.

Abstract translation: 故障修复功能体现在半导体结构中，其中通过形成用于生长单晶层的柔性衬底，使单质材料的高质量外延层制成覆盖在诸如大硅晶片的单晶衬底上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 在一个实例中通过识别故障的存在并且在另一个实例中通过提供故障校正来进行故障补救。 故障修复功能可以与传统的数据发射电路组合以形成具有公共衬底的整体结构。

公开(公告)号：US20030034502A1

公开(公告)日：2003-02-20

申请号：US09930259

申请日：2001-08-16

Applicant: MOTOROLA, INC.

Inventor： Mihir A. Pandya ,  Raymond B. Essick IV ,  David P. Gurney

IPC: H01L029/74

CPC classification number: H01L21/8258 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L27/0605

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. Furthermore, a pre-computation unit is implemented in the compound semiconductor material to pre-compute instructions directly in the memory system, thereby resulting in substantially increased processing throughput.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。 此外，在化合物半导体材料中实现预计算单元以直接在存储器系统中计算指令，从而导致大大增加的处理吞吐量。

公开(公告)号：US20030034488A1

公开(公告)日：2003-02-20

申请号：US09930175

申请日：2001-08-16

Applicant: MOTOROLA, INC.

Inventor： Peter J. Wilson ,  Raymond B. Essick ,  Mihir A. Pandya

IPC: H01L029/06

CPC classification number: H01L21/8258 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L27/0605

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart form a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. These materials and techniques can be utilized to fabricate and facilitate a dataflow processor that achieves improved execution unit duty cycle performance and deterministic execution performance for at least some dataflow tokens.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括由氧化硅的非晶界面层隔开形成硅晶片的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。 这些材料和技术可用于制造和促进实现改进的执行单位占空比性能和至少一些数据流令牌的确定性执行性能的数据流处理器。

公开(公告)号：US20030016067A1

公开(公告)日：2003-01-23

申请号：US09909938

申请日：2001-07-23

Applicant: MOTOROLA, INC.

Inventor： Peter J. Wilson ,  Mihir A. Pandya

IPC: G06F001/04

CPC classification number: G06F1/10

Abstract: A system employing synchronous clock signals utilizes the distribution of a fast clock signal along a forward path to clock generators for providing standard clock signals, and a recovery of such signal via a return path. The fast clock signal has a distinguishable portion, such as a periodic missing pulse or other anomaly, which is used to determine delay characteristics for the fast clock signal to the clock generators. A controllable delay corresponding to the forward path is adjusted, based on the determined delay characteristics, to synchronize delivery of the fast clock signal to the clock generators. Preferably, a significant portion of the clock generation and distribution system is formed on a semiconductor structure have a combination of compound semiconductor material and Group IV semiconductor material.

Abstract translation: 采用同步时钟信号的系统利用沿着正向路径的快速时钟信号的分布到时钟发生器以提供标准时钟信号，以及通过返回路径恢复这种信号。 快速时钟信号具有可区分的部分，例如周期性丢失脉冲或其他异常，其用于确定到时钟发生器的快速时钟信号的延迟特性。 基于确定的延迟特性来调整对应于前向路径的可控延迟，以将快速时钟信号的同步传送到时钟发生器。 优选地，时钟发生和分配系统的重要部分形成在半导体结构上，其具有化合物半导体材料和IV族半导体材料的组合。

公开(公告)号：US20030034508A1

公开(公告)日：2003-02-20

申请号：US09930247

申请日：2001-08-16

Applicant: MOTOROLA, INC.

Inventor： Mihir A. Pandya

IPC: H01L029/76

CPC classification number: G06F7/5446 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8258 ,  H01L27/0605

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying a monocrystalline substrate of a semiconductor structure by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. A semiconductor structure formed in accordance with this method includes a monocrystalline silicon substrate, a metal oxide semiconductor portion formed in the monocrystalline silicon substrate, and a compound semiconductor portion formed in the layer of monocrystalline compound semiconductor material. A circuit such as a microprocessor is formed in the complementary metal oxide semiconductor (CMOS) portion, and a coordinate rotation digital computer (CORDIC) functional unit formed in the compound semiconductor portion. The CORDIC algorithms are thus performed in a high speed compound semiconductor structure such as Gallium Arsenide (GaAs) which is integrated with a CMOS microprocessor on a common substrate.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在半导体结构的单晶衬底上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 根据该方法形成的半导体结构包括单晶硅衬底，形成在单晶硅衬底中的金属氧化物半导体部分和形成在单晶化合物半导体材料层中的化合物半导体部分。 在互补金属氧化物半导体（CMOS）部分中形成诸如微处理器的电路，以及形成在化合物半导体部分中的坐标旋转数字计算机（CORDIC）功能单元。 因此，CORDIC算法在诸如砷化镓（GaAs）的高速化合物半导体结构中进行，其在公共衬底上与CMOS微处理器集成。

公开(公告)号：US20030034506A1

公开(公告)日：2003-02-20

申请号：US09930276

申请日：2001-08-16

Applicant: MOTOROLA, INC.

Inventor： Mihir A. Pandya ,  Peter J. Wilson

IPC: H01L031/0328

CPC classification number: H01L27/0605 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8258

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. Furthermore, a small, high performance scheduling engine is implemented in the compound semiconductor material to take advantage of the higher frequency of operation to increase determinism and to reduce response times.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。 此外，在化合物半导体材料中实施小型高性能调度引擎以利用较高的操作频率来增加确定性并减少响应时间。