公开(公告)号：US20190052226A1

公开(公告)日：2019-02-14

申请号：US15672251

申请日：2017-08-08

Applicant: MOTOROLA SOLUTIONS, INC.

Inventor： Mark Rozental ,  Claudine Tordjman ,  Richard S. Young ,  Uri Vallach

IPC: H03B5/36 ,  H03L7/06 ,  H03L7/24

Abstract: Method and apparatus for determining a clock frequency for an electronic processor are provided. One embodiment provides a clock generator for determining a clock frequency for an electronic processor and providing a clock signal to the electronic processor. The clock generator includes a crystal oscillator producing a reference signal and a phase locked loop receiving the reference signal and configured to generate the clock signal based on the reference signal. The clock generator also includes a tuning logic controller electrically coupled to the phase locked loop. The tuning logic controller is configured to program the phase locked loop to a first frequency and determine an integrated circuit process corner of the electronic processor. The tuning logic controller is also configured to determine a second frequency based on the integrated circuit process corner and program the phase locked loop to the second frequency.

公开(公告)号：US09407477B2

公开(公告)日：2016-08-02

申请号：US14539490

申请日：2014-11-12

Applicant: MOTOROLA SOLUTIONS, INC

Inventor： Mark Rozental ,  Nir Corse ,  Kevin G. Doberstein ,  Josh E. Dorevitch ,  Baruh Hason ,  Claudine Tordjman

IPC: H04L25/06 ,  H04B1/10

CPC classification number: H04L25/061 ,  H04B1/10 ,  H04B1/30 ,  H04B2001/305

Abstract: A method and apparatus for a method and apparatus for correlation canceller for interference mitigation with adaptive DC offset cancellation for a dual mode communication device includes detecting an active signal transmitting in one mode; configuring integrators associated with the adaptive correlation canceller into gain amplifiers; detecting DC offset utilizing the gain amplifiers and comparators; and configuring the integrators from the gain amplifiers back to integrators with the DC offset applied thereto. The active signal transmitting in one mode can be Long Term Evolution (LTE) which is adjacent to a signal in another mode.

Abstract translation: 一种用于双模式通信设备的自适应DC偏移消除用于干扰减轻的相关消除器的方法和装置，包括：检测在一种模式下发送的有源信号; 将与自适应相关消除器相关联的积分器配置成增益放大器; 利用增益放大器和比较器检测DC偏移; 以及将来自增益放大器的积分器配置为具有施加到其的DC偏移的积分器。 以一种模式发送的活动信号可以是与另一模式中的信号相邻的长期演进（LTE）。

公开(公告)号：US09602115B1

公开(公告)日：2017-03-21

申请号：US15174871

申请日：2016-06-06

Applicant: MOTOROLA SOLUTIONS, INC.

Inventor： Mark Rozental ,  Ricardo Franco ,  Claudine Tordjman ,  Richard S. Young

IPC: H03L7/06 ,  H03L7/099 ,  H03L7/093 ,  H03L7/095 ,  H03L7/089 ,  H03K5/15 ,  H03L7/18

CPC classification number: H03L7/0996 ,  H03K5/15046 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/095 ,  H03L7/0995 ,  H03L7/0997 ,  H03L7/18 ,  H03L7/1806

Abstract: A method and device for generating a multi-rate clock signal using a ring voltage-controlled oscillator based phase-locked loop is provided. The device includes a delay line having a length extending beyond a predetermined length required for operation of the phase-locked loop. The device further includes a tap tuning logic circuit coupled to the delay line. The delay line receives an input signal and a tuning voltage from the phase frequency detector, charge pump and loop filter circuits and generates a plurality of tapped output signals. The plurality of tapped output signals is received by the integrated digital multi-rate clock generator configured to create a plurality of clock signals.