公开(公告)号：US20190052226A1

公开(公告)日：2019-02-14

申请号：US15672251

申请日：2017-08-08

申请人： MOTOROLA SOLUTIONS, INC.

发明人： Mark Rozental ,  Claudine Tordjman ,  Richard S. Young ,  Uri Vallach

IPC分类号： H03B5/36 ,  H03L7/06 ,  H03L7/24

摘要： Method and apparatus for determining a clock frequency for an electronic processor are provided. One embodiment provides a clock generator for determining a clock frequency for an electronic processor and providing a clock signal to the electronic processor. The clock generator includes a crystal oscillator producing a reference signal and a phase locked loop receiving the reference signal and configured to generate the clock signal based on the reference signal. The clock generator also includes a tuning logic controller electrically coupled to the phase locked loop. The tuning logic controller is configured to program the phase locked loop to a first frequency and determine an integrated circuit process corner of the electronic processor. The tuning logic controller is also configured to determine a second frequency based on the integrated circuit process corner and program the phase locked loop to the second frequency.

公开(公告)号：US09602115B1

公开(公告)日：2017-03-21

申请号：US15174871

申请日：2016-06-06

申请人： MOTOROLA SOLUTIONS, INC.

发明人： Mark Rozental ,  Ricardo Franco ,  Claudine Tordjman ,  Richard S. Young

IPC分类号： H03L7/06 ,  H03L7/099 ,  H03L7/093 ,  H03L7/095 ,  H03L7/089 ,  H03K5/15 ,  H03L7/18

CPC分类号： H03L7/0996 ,  H03K5/15046 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/095 ,  H03L7/0995 ,  H03L7/0997 ,  H03L7/18 ,  H03L7/1806

摘要： A method and device for generating a multi-rate clock signal using a ring voltage-controlled oscillator based phase-locked loop is provided. The device includes a delay line having a length extending beyond a predetermined length required for operation of the phase-locked loop. The device further includes a tap tuning logic circuit coupled to the delay line. The delay line receives an input signal and a tuning voltage from the phase frequency detector, charge pump and loop filter circuits and generates a plurality of tapped output signals. The plurality of tapped output signals is received by the integrated digital multi-rate clock generator configured to create a plurality of clock signals.

公开(公告)号：US09735759B1

公开(公告)日：2017-08-15

申请号：US15095644

申请日：2016-04-11

申请人： MOTOROLA SOLUTIONS, INC.

发明人： Edward A. Diaz ,  Johnny R. Ferreira ,  Ricardo Franco ,  Charles R. Ruelke ,  Richard S. Young

IPC分类号： H03K3/00 ,  H03K3/013 ,  H03K3/66 ,  H03K5/1534

CPC分类号： H03K3/013 ,  H03K3/66 ,  H03K5/1534 ,  H03K19/00346 ,  H03M1/0818 ,  H03M1/0872 ,  H03M1/12

摘要： A method and apparatus for mitigating electromagnetic noise in an electronic device. The method includes generating a trigger clock signal at a first frequency, and generating a second clock signal at a second frequency. The second frequency is higher than the first frequency. The method also includes receiving an input signal with a converter circuit, detecting an event based on the trigger clock signal, and predicting a time for a conversion of the input signal based on the detected event. The method further includes blanking the second clock signal for a predetermined period based on the predicted time for a conversion.