公开(公告)号：US20180074955A1

公开(公告)日：2018-03-15

申请号：US15486394

申请日：2017-04-13

申请人： MStar Semiconductor, Inc.

发明人： CHUN-CHIEH WANG

IPC分类号： G06F12/06 ,  H04N21/232

CPC分类号： G06F12/0646 ,  G06F12/0607 ,  G06F2212/1024 ,  G06F2212/174 ,  H03M13/276 ,  H03M13/2764 ,  H03M13/2782 ,  H03M13/6552 ,  H04N21/2326 ,  H04N21/426 ,  H04N21/4382

摘要： A time de-interleaving circuit is located at a signal receiver of a communication system to perform a time de-interleaving process on an interleaved signal. The interleaved signal includes a plurality of information units, which include a plurality of data units and a plurality of common units. The time de-interleaving circuit includes: a data unit access address generator, generating a plurality of data unit access addresses according to a first address sequence to accordingly access the plurality of data units in a memory; and a common unit access address generator, generating a plurality of common unit access addresses according to a second address sequence to accordingly access the plurality of common units in the memory. The second address sequence is a reverse sequence of the first address sequence.

公开(公告)号：US20180077447A1

公开(公告)日：2018-03-15

申请号：US15695345

申请日：2017-09-05

申请人： MStar Semiconductor, Inc.

发明人： CHUN-CHIEH WANG

IPC分类号： H04N21/4385 ,  H03M13/27 ,  H04N21/44 ,  H04N21/426 ,  H04N21/6402

CPC分类号： H04N21/4385 ,  G06F12/0607 ,  H03M13/2703 ,  H03M13/2735 ,  H03M13/2764 ,  H03M13/2782 ,  H03M13/2785 ,  H03M13/6552 ,  H04N21/426 ,  H04N21/42692 ,  H04N21/4382 ,  H04N21/44004 ,  H04N21/6402

摘要： A de-interleaving circuit that performs a time de-interleaving process on an interleaved block of an interleave signal includes: an input buffer, buffering multiple information units included in a time interleaved block; a writing address generator, generating multiple writing addresses according to a predetermined rule to write the information units buffered in the input buffer to a memory; a reading address generator, generating multiple reading addresses according to the predetermined rule to read the information units from the memory; and an output buffer, buffering the information units read from the memory. The information units are stored in multiple tiles of the memory. The tiles correspond to multiple regions of the time interleaved block, the multiple regions include a first region and a second region, and the dimensions of each tile in the first region are different from the dimensions of each tile in the second region.

公开(公告)号：US20170359208A1

公开(公告)日：2017-12-14

申请号：US15459142

申请日：2017-03-15

申请人： MStar Semiconductor, Inc.

发明人： CHUN-CHIEH WANG

IPC分类号： H04L27/26 ,  H04L29/06

CPC分类号： H04L27/2649 ,  H03M13/00 ,  H04L1/0043 ,  H04L1/0071 ,  H04L69/22

摘要： A time de-interleaving circuit and a time de-interleaving method perform a time de-interleaving process through writing and reading a plurality of sets of time interleaved data into and from a first memory and a second memory. The time de-interleaving method includes: selecting a set of first time interleaved data and a set of second time interleaved data from the plurality of sets of time interleaved data, the set of first time interleaved data and the set of second time interleaved data having the same delay length; writing the set of first time interleaved data into the first memory; and writing the set of second time interleaved data into the second memory. The first memory utilizes a bit length as an access unit, and the second memory has an access unit smaller than the bit width.

公开(公告)号：US20170212682A1

公开(公告)日：2017-07-27

申请号：US15399120

申请日：2017-01-05

申请人： MStar Semiconductor, Inc.

发明人： CHUN-CHIEH WANG

IPC分类号： G06F3/06

CPC分类号： G06F3/064 ,  G06F3/0619 ,  G06F3/0659 ,  H03M13/2778 ,  H03M13/2785 ,  H04L1/0045 ,  H04L1/0052 ,  H04L1/0071

摘要： A time de-interleaving method is applied to a signal receiver of a communication system to perform a time de-interleaving process on an interleaved signal. The interleaved signal includes a first time interleaved block and a second time interleaved block. The time de-interleaving method includes: reading a first part of cells of the first time interleaved block from a memory; releasing a memory space corresponding to the first part of the cells in the memory; and writing a second part of cells of the second time interleaved block into the memory space before the first time interleaved block is completely read out from memory.

公开(公告)号：US20180234727A1

公开(公告)日：2018-08-16

申请号：US15883136

申请日：2018-01-30

申请人： MStar Semiconductor, Inc.

发明人： CHUN-CHIEH WANG

IPC分类号： H04N21/443 ,  H04N21/61 ,  H04N21/2315 ,  H04N21/433 ,  H04N21/426 ,  H04N21/438

CPC分类号： H04N21/4435 ,  H04L27/2649 ,  H04N21/2315 ,  H04N21/42615 ,  H04N21/433 ,  H04N21/4382 ,  H04N21/6112 ,  H04N21/6118

摘要： A data processing method applied to a multiplexing process and a bit de-interleaving process of a digital television is provided. The data processing method includes: storing a target OFDM symbol of OFDM symbols; generating a write address for each data bit of the target OFDM symbol according a sequence number of target OFDM symbol; generating a read address for each data bit of the target OFDM symbol according to a counter value; and writing each data bit of the target OFDM symbol into a memory according to the write addresses, and reading each data bit of the target OFDM symbol from the memory according to the read addresses. Each data bit of the target symbol is subjected to one write operation and one read operation. The target OFDM symbol read from the memory has completely undergone the multiplexing process and the bit de-interleaving process.