公开(公告)号：USRE47803E1

公开(公告)日：2020-01-07

申请号：US14995059

申请日：2016-01-13

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

IPC: G11C7/10 ,  G11C7/22

Abstract: An integrated circuit includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device using a first input/output pin and a second input/output pin concurrently. In an embodiment, the read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first input/output pin, and the second address bit being transmitted using the second input/output pin. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The method includes transferring the data from the memory device using the first input/output pin and the second input/output pin concurrently.

公开(公告)号：US20180373625A1

公开(公告)日：2018-12-27

申请号：US15629845

申请日：2017-06-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chia-He Liu ,  Jian-Shing Liu

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0246 ,  G06F11/00 ,  G06F13/1668 ,  G06F2212/1036 ,  G06F2212/7209

Abstract: A memory device and associated control method are provided. The memory device includes a memory array and a control circuit, which are electrically connected with each other. The memory array includes a plurality of memory groups. A first memory group among the plurality of memory groups includes at least one first memory unit. The control circuit executes the control method including following steps. Firstly, a first timestamp corresponding to a first time point is recorded when one of the at least one first memory unit is programmed. Then, state of the first memory group is identified based on the first timestamp and an identification rule, and the first memory group is retired when a condition being predefined in the identification rule is satisfied.

公开(公告)号：US10459836B2

公开(公告)日：2019-10-29

申请号：US15629845

申请日：2017-06-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chia-He Liu ,  Jian-Shing Liu

IPC: G06F12/00 ,  G06F12/02 ,  G06F13/16 ,  G06F11/00

Abstract: A memory device and associated control method are provided. The memory device includes a memory array and a control circuit, which are electrically connected with each other. The memory array includes a plurality of memory groups. A first memory group among the plurality of memory groups includes at least one first memory unit. The control circuit executes the control method including following steps. Firstly, a first timestamp corresponding to a first time point is recorded when one of the at least one first memory unit is programmed. Then, state of the first memory group is identified based on the first timestamp and an identification rule, and the first memory group is retired when a condition being predefined in the identification rule is satisfied.

公开(公告)号：US20140237207A1

公开(公告)日：2014-08-21

申请号：US14264013

申请日：2014-04-28

Applicant: Macronix International Co., Ltd.

Inventor： CHUNG-HSIUNG HUNG ,  Kuen-Long Chang ,  Chia-He Liu

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F12/00 ,  G06F13/4286

Abstract: A method of conducting an operation in an integrated circuit having a plurality of memory cells includes receiving an operating command for the memory cells and receiving a first address segment associated with the memory cells in at least one clock cycle after receiving the operating command. The method further includes receiving a first performance enhancement indicator in at least one clock cycle after ending the first address segment while before starting to transfer data, for determining whether an enhanced operation is to be performed.

Abstract translation: 在具有多个存储单元的集成电路中执行操作的方法包括在接收到操作命令之后的至少一个时钟周期中接收用于存储器单元的操作命令并接收与存储器单元相关联的第一地址段。 该方法还包括在开始传送数据之前，在结束第一地址段之后的至少一个时钟周期内接收第一性能增强指示符，以确定是否执行增强的操作。

公开(公告)号：US08738849B2

公开(公告)日：2014-05-27

申请号：US13686917

申请日：2012-11-28

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

IPC: G06F12/00

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F12/00 ,  G06F13/4286

Abstract: A method of conducting an operation in an integrated circuit having a plurality of memory cells includes receiving an operating command for the memory cells and receiving a first address segment associated with the memory cells in at least one clock cycle after receiving the operating command. The method further includes receiving a first performance enhancement indicator in at least one clock cycle after ending the first address segment while before starting to transfer data, for determining whether an enhanced operation is to be performed.

Abstract translation: 在具有多个存储单元的集成电路中执行操作的方法包括在接收到操作命令之后的至少一个时钟周期中接收用于存储器单元的操作命令并接收与存储器单元相关联的第一地址段。 该方法还包括在开始传送数据之前，在结束第一地址段之后的至少一个时钟周期内接收第一性能增强指示符，以确定是否执行增强的操作。

公开(公告)号：USRE49125E1

公开(公告)日：2022-07-05

申请号：US16734882

申请日：2020-01-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

IPC: G11C7/10 ,  G11C7/22

Abstract: An integrated circuit includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device using a first input/output pin and a second input/output pin concurrently. In an embodiment, the read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first input/output pin, and the second address bit being transmitted using the second input/output pin. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The method includes transferring the data from the memory device using the first input/output pin and the second input/output pin concurrently.

公开(公告)号：US20130086350A1

公开(公告)日：2013-04-04

申请号：US13686917

申请日：2012-11-28

Applicant: Macronix International Co., Ltd.

Inventor： CHUNG-HSIUNG HUNG ,  Kuen-Long Chang ,  Chia-He Liu

IPC: G06F12/00

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F12/00 ,  G06F13/4286

Abstract: A method of conducting an operation in an integrated circuit having a plurality of memory cells includes receiving an operating command for the memory cells and receiving a first address segment associated with the memory cells in at least one clock cycle after receiving the operating command. The method further includes receiving a first performance enhancement indicator in at least one clock cycle after ending the first address segment while before starting to transfer data, for determining whether an enhanced operation is to be performed.

Abstract translation: 在具有多个存储单元的集成电路中执行操作的方法包括在接收到操作命令之后的至少一个时钟周期中接收用于存储器单元的操作命令并接收与存储器单元相关联的第一地址段。 该方法还包括在开始传送数据之前，在结束第一地址段之后的至少一个时钟周期内接收第一性能增强指示符，以确定是否执行增强的操作。