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Patent Agency Ranking
公开(公告)号：US08976600B2
公开(公告)日：2015-03-10
申请号：US14046428
申请日：2013-10-04
Applicant: Macronix International Co., Ltd.
Inventor： Chun-Hsiung Hung , Ti Wen Chen , Shuo-Nan Hung , Shih-Lin Huang
Abstract: A memory circuit includes word lines coupled to a memory array, including a first set of one or more word lines deselected in an erase operation, and a second set of one or more word lines selected in the erase operation. Control circuitry couples the first set of one or more word lines deselected in the erase operation to a reference voltage, responsive to receiving an erase command for the erase operation. Some examples further include a first transistor that switchably couples a word line to a global word line, and a second transistor that switchably couples the word line to a ground voltage. The control circuitry is coupled to the first transistor and the second transistor, wherein the control circuitry has a plurality of modes including at least an erase operation. In a first mode, the first transistor couples the word line to the global word line, and the second transistor decouples the word line from the ground voltage. In a second mode, the first transistor decouples the word line from the global word line, and the second transistor couples the word line to the ground voltage.
Abstract translation: 存储电路包括耦合到存储器阵列的字线，包括在擦除操作中取消选择的一个或多个字线的第一组以及在擦除操作中选择的一个或多个字线的第二组。 响应于接收到擦除操作的擦除命令，控制电路将擦除操作中未选择的一个或多个字线的第一组耦合到参考电压。 一些示例还包括可将字线可切换地耦合到全局字线的第一晶体管，以及可切换地将字线耦合到接地电压的第二晶体管。 控制电路耦合到第一晶体管和第二晶体管，其中控制电路具有包括至少擦除操作的多个模式。 在第一模式中，第一晶体管将字线耦合到全局字线，并且第二晶体管将字线与接地电压分离。 在第二模式中，第一晶体管将字线与全局字线分离，并且第二晶体管将字线耦合到接地电压。
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公开(公告)号：US08982628B2
公开(公告)日：2015-03-17
申请号：US14176794
申请日：2014-02-10
Applicant: Macronix International Co., Ltd.
Inventor： Shuo-Nan Hung , Ti Wen Chen
CPC classification number: G11C16/26 , G11C29/785
Abstract: Regardless of data values stored on data memory cells, all read operations on the data memory cells are disallowed. For example, current flow is disallowed through a string of the data memory cells and one or more select line memory cells. The particular select value stored in a first select line memory cell in the string, for example coupled to a ground select line or a string select line, determines whether the string is enabled or disabled.
Abstract translation: 不管存储在数据存储单元上的数据值如何，都不允许对数据存储单元进行所有读操作。 例如，通过一串数据存储单元和一个或多个选择行存储单元不允许当前流。 存储在字符串中的第一选择行存储单元中的特定选择值，例如耦合到接地选择线或字符串选择行，确定字符串是启用还是禁用。
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公开(公告)号：US09672920B2
公开(公告)日：2017-06-06
申请号：US14657084
申请日：2015-03-13
Applicant: Macronix International Co., Ltd.
Inventor： Chih-Chang Hsieh , Ti Wen Chen , Yungchun Li , Hang Ting Lue
CPC classification number: G11C16/10 , G11C16/3427 , G11C16/3459
Abstract: This disclosure provides a memory device. The memory device includes a plurality of memory cells and a control circuit coupled to the memory cells. The control circuit is configured to provide a first programming voltage to the memory cells; verify the memory cells against an interim level verify voltage to divide the memory cells into a first group of memory cells and a second group of memory cells according to whether the memory cells do not reach or do reach the interim level verify voltage, respectively; provide a second programming voltage to the first group of memory cells and inhibit the second group of memory cells from receiving the second programming voltage, the second programming voltage being greater than or equal to the first programming voltage; and verify the first group of memory cells and the second group of memory cells against a desired level voltage.
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公开(公告)号：US20140254284A1
公开(公告)日：2014-09-11
申请号：US14046428
申请日：2013-10-04
Applicant: Macronix International Co., Ltd.
Inventor： Chun-Hsiung Hung , Ti Wen Chen , Shuo-Nan Hung , Shih-Lin Huang
IPC: G11C16/16
Abstract: A memory circuit includes word lines coupled to a memory array, including a first set of one or more word lines deselected in an erase operation, and a second set of one or more word lines selected in the erase operation. Control circuitry couples the first set of one or more word lines deselected in the erase operation to a reference voltage, responsive to receiving an erase command for the erase operation. Some examples further include a first transistor that switchably couples a word line to a global word line, and a second transistor that switchably couples the word line to a ground voltage. The control circuitry is coupled to the first transistor and the second transistor, wherein the control circuitry has a plurality of modes including at least an erase operation. In a first mode, the first transistor couples the word line to the global word line, and the second transistor decouples the word line from the ground voltage. In a second mode, the first transistor decouples the word line from the global word line, and the second transistor couples the word line to the ground voltage.
Abstract translation: 存储器电路包括耦合到存储器阵列的字线，包括在擦除操作中取消选择的一个或多个字线的第一组以及在擦除操作中选择的一个或多个字线的第二组。 响应于接收到擦除操作的擦除命令，控制电路将擦除操作中未选择的一个或多个字线的第一组耦合到参考电压。 一些示例还包括可将字线可切换地耦合到全局字线的第一晶体管，以及可切换地将字线耦合到接地电压的第二晶体管。 控制电路耦合到第一晶体管和第二晶体管，其中控制电路具有包括至少擦除操作的多个模式。 在第一模式中，第一晶体管将字线耦合到全局字线，并且第二晶体管将字线与接地电压分离。 在第二模式中，第一晶体管将字线与全局字线分离，并且第二晶体管将字线耦合到接地电压。
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公开(公告)号：US20140160849A1
公开(公告)日：2014-06-12
申请号：US14176794
申请日：2014-02-10
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Shuo-Nan Hung , Ti Wen Chen
IPC: G11C16/26
CPC classification number: G11C16/26 , G11C29/785
Abstract: Regardless of data values stored on data memory cells, all read operations on the data memory cells are disallowed. For example, current flow is disallowed through a string of the data memory cells and one or more select line memory cells. The particular select value stored in a first select line memory cell in the string, for example coupled to a ground select line or a string select line, determines whether the string is enabled or disabled.
Abstract translation: 不管存储在数据存储单元上的数据值如何，都不允许对数据存储单元进行所有读操作。 例如，通过一串数据存储单元和一个或多个选择行存储单元不允许当前流。 存储在字符串中的第一选择行存储单元中的特定选择值，例如耦合到接地选择线或字符串选择行，确定字符串是启用还是禁用。
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