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公开(公告)号:US09536808B1
公开(公告)日:2017-01-03
申请号:US14741087
申请日:2015-06-16
Applicant: Macronix International Co., Ltd.
Inventor: Zheng-Chang Mu , Cheng-Wei Lin , Kuang-Wen Liu
IPC: H01L29/40 , H01L23/48 , H01L23/528 , H01L21/768
CPC classification number: H01L21/76816 , H01L21/31111 , H01L21/31144 , H01L21/3212 , H01L21/7684 , H01L21/76877 , H01L23/481 , H01L23/5226 , H01L24/03 , H01L24/05 , H01L2224/0361 , H01L2224/05089 , H01L2924/00014 , H01L2224/05599
Abstract: Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.
Abstract translation: 提供具有大通孔(例如焊盘下方)的半导体器件,以增加通孔开口面积比,增加通孔蚀刻速率,避免金属间电介质破裂和对集成电路的损坏。 通孔被定义为在隔离的导电底部基底层和导电顶层之间的金属间介电层中的大的开放区域。 还提供了制造具有大通孔的半导体器件的方法。
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公开(公告)号:US09741607B2
公开(公告)日:2017-08-22
申请号:US15351774
申请日:2016-11-15
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor: Zheng-Chang Mu , Cheng-Wei Lin , Kuang-Wen Liu
IPC: H01L21/44 , H01L21/768 , H01L23/48 , H01L21/311 , H01L21/321
CPC classification number: H01L21/76816 , H01L21/31111 , H01L21/31144 , H01L21/3212 , H01L21/7684 , H01L21/76877 , H01L23/481 , H01L23/5226 , H01L24/03 , H01L24/05 , H01L2224/0361 , H01L2224/05089 , H01L2924/00014 , H01L2224/05599
Abstract: Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.
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