公开(公告)号：US20060119991A1

公开(公告)日：2006-06-08

申请号：US10525488

申请日：2003-08-04

申请人： Manish Garg ,  Kiran Batni Rao ,  Jose Pineda De Gyvez

发明人： Manish Garg ,  Kiran Batni Rao ,  Jose Pineda De Gyvez

IPC分类号： H02H7/00

CPC分类号： G11C5/143 ,  G11C5/14

摘要： A method for reducing the power consumption in a state retaining circuit during a standby mode is disclosed comprising, in an active state, providing a regular power supply (VDD) and a standby power supply (VDD STANDBY) to the state retaining circuit; for a transition from an active state to a standby state, decreasing the regular power supply to ground level and maintaining the standby power supply (VDD STANDBY) thus providing the circuit elements (36, 142, 78, 85) of the state retaining circuit with enough power for retaining the state during standby mode; and for a transition from the standby state to the active state, increasing the regular power supply (VDD) from its ground level to its active level. A circuit for reducing the power consumption in a state retaining circuit during a standby mode is disclosed comprising a control unit (1) providing at least one control signal; a data input unit (3) providing at least one input signal; a data output unit (7) providing at least one output signal; a data storage unit (5) for holding the state of the circuit during an a standby mode; a regular power supply supplying power to the data storage unit (5) during an active mode; and a standby power supply supplying power to at least a part of the data storage unit (5) during the active mode and the standby mode.

摘要翻译： 公开了一种用于在待机模式期间降低状态保持电路中的功耗的方法，包括：在有源状态下，向状态保持电路提供常规电源（VDD）和待机电源（VDD STANDBY）; 为了从活动状态转变到待机状态，将正常电源降低到接地电平并维持待机电源（VDD STANDBY），从而将状态保持电路的电路元件（36,142,78,85）与 在待机模式下保持状态的足够的电力; 并且为了从待机状态转换到有效状态，将常规电源（VDD）从其地电平增加到其有效电平。 公开了一种用于在备用模式期间降低状态保持电路中的功耗的电路，包括：提供至少一个控制信号的控制单元（1） 提供至少一个输入信号的数据输入单元（3）; 提供至少一个输出信号的数据输出单元（7）; 数据存储单元，用于在待机模式期间保持电路的状态; 在活动模式期间向数据存储单元（5）供电的常规电源; 以及在活动模式和待机模式期间向数据存储单元（5）的至少一部分供电的备用电源。

公开(公告)号：US20050174161A1

公开(公告)日：2005-08-11

申请号：US10502183

申请日：2002-12-18

申请人： Hendricus Veendrick ,  Rinze Ida Meijer ,  Kiran Batni Rao

发明人： Hendricus Veendrick ,  Rinze Ida Meijer ,  Kiran Batni Rao

IPC分类号： H01L21/822 ,  H01L27/04 ,  H03K19/00 ,  H03K19/0948 ,  H03K17/687

CPC分类号： H03K19/0016 ,  Y10T307/832

摘要： An integrated circuit (100) has a circuit portion (102) that can be switched to a standby mode through an enable transistor (104), which is coupled between an internal power supply line (120) and an external power supply line (130). The enable transistor (104) is controlled by control circuitry via a control line (160). The control line (160) is coupled to the gates of a first transistor (152) and a further transistor (154) of a logic gate (150). The substrate of the further transistor (154) is coupled to a backbias generator (170). Consequently, when the enable transistor (104) is switched off, the further transistor (154) is enabled and applies a substantial backbias to the gate of the enable transistor (104), thus dramatically reducing the leakage current from the circuit portion (102) through the enable transistor (104).

摘要翻译： 集成电路（100）具有电路部分（102），其可以通过耦合在内部电源线（120）和外部电源线（130）之间的使能晶体管（104）切换到待机模式， 。 使能晶体管（104）由控制电路经由控制线（160）控制。 控制线（160）耦合到逻辑门（150）的第一晶体管（152）和另一晶体管（154）的栅极。 另一个晶体管（154）的衬底耦合到回流发生器（170）。 因此，当使能晶体管（104）关断时，另一个晶体管（154）被使能并且向使能晶体管（104）的栅极施加实质的反向比，从而显着地减少来自电路部分（102）的漏电流， 通过使能晶体管（104）。