公开(公告)号：US20060119991A1

公开(公告)日：2006-06-08

申请号：US10525488

申请日：2003-08-04

申请人： Manish Garg ,  Kiran Batni Rao ,  Jose Pineda De Gyvez

发明人： Manish Garg ,  Kiran Batni Rao ,  Jose Pineda De Gyvez

IPC分类号： H02H7/00

CPC分类号： G11C5/143 ,  G11C5/14

摘要： A method for reducing the power consumption in a state retaining circuit during a standby mode is disclosed comprising, in an active state, providing a regular power supply (VDD) and a standby power supply (VDD STANDBY) to the state retaining circuit; for a transition from an active state to a standby state, decreasing the regular power supply to ground level and maintaining the standby power supply (VDD STANDBY) thus providing the circuit elements (36, 142, 78, 85) of the state retaining circuit with enough power for retaining the state during standby mode; and for a transition from the standby state to the active state, increasing the regular power supply (VDD) from its ground level to its active level. A circuit for reducing the power consumption in a state retaining circuit during a standby mode is disclosed comprising a control unit (1) providing at least one control signal; a data input unit (3) providing at least one input signal; a data output unit (7) providing at least one output signal; a data storage unit (5) for holding the state of the circuit during an a standby mode; a regular power supply supplying power to the data storage unit (5) during an active mode; and a standby power supply supplying power to at least a part of the data storage unit (5) during the active mode and the standby mode.

摘要翻译： 公开了一种用于在待机模式期间降低状态保持电路中的功耗的方法，包括：在有源状态下，向状态保持电路提供常规电源（VDD）和待机电源（VDD STANDBY）; 为了从活动状态转变到待机状态，将正常电源降低到接地电平并维持待机电源（VDD STANDBY），从而将状态保持电路的电路元件（36,142,78,85）与 在待机模式下保持状态的足够的电力; 并且为了从待机状态转换到有效状态，将常规电源（VDD）从其地电平增加到其有效电平。 公开了一种用于在备用模式期间降低状态保持电路中的功耗的电路，包括：提供至少一个控制信号的控制单元（1） 提供至少一个输入信号的数据输入单元（3）; 提供至少一个输出信号的数据输出单元（7）; 数据存储单元，用于在待机模式期间保持电路的状态; 在活动模式期间向数据存储单元（5）供电的常规电源; 以及在活动模式和待机模式期间向数据存储单元（5）的至少一部分供电的备用电源。

公开(公告)号：US08730713B2

公开(公告)日：2014-05-20

申请号：US13551658

申请日：2012-07-18

申请人： Manish Garg ,  Michael ThaiThanh Phan

发明人： Manish Garg ,  Michael ThaiThanh Phan

IPC分类号： G11C11/00

CPC分类号： G11C7/04 ,  G11C8/16 ,  G11C11/413 ,  G11C11/417 ,  G11C11/418 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/24

摘要： Systems and methods for detecting and improving writeability of a static random access memory (SRAM) cell. A bias voltage value corresponding to an operating condition, such as, a process, a voltage, or a temperature operation condition that indicates a cell write failure condition of an external SRAM array comprising the SRAM cell is generated. This bias voltage value is applied to word lines of SRAM cells in a model SRAM array. A first delay for a trigger signal rippled through the model SRAM array is detected and compared to a reference delay. A write assist indication is generated if the first delay is greater than or equal to the reference delay. Based on the write assist indication, a write assist is provided to the SRAM cell.

摘要翻译： 用于检测和改善静态随机存取存储器（SRAM）单元的可写性的系统和方法。 产生对应于指示包括SRAM单元的外部SRAM阵列的单元写入故障状态的工作状态，例如工艺，电压或温度操作条件的偏置电压值。 该偏置电压值被施加到模型SRAM阵列中的SRAM单元的字线。 检测到通过型号SRAM阵列波纹的触发信号的第一延迟，并将其与参考延迟进行比较。 如果第一延迟大于或等于参考延迟，则产生写辅助指示。 基于写入辅助指示，向SRAM单元提供写入辅助。

公开(公告)号：US20130046836A1

公开(公告)日：2013-02-21

申请号：US13213320

申请日：2011-08-19

申请人： Patrick Tousignant ,  Manish Garg ,  Sridhar Sundararaman

发明人： Patrick Tousignant ,  Manish Garg ,  Sridhar Sundararaman

IPC分类号： G06F15/16

CPC分类号： H04L51/16

摘要： Web-based email systems are enabled to synchronize conversations and conversation properties. Conversations are enumerated to new clients providing folder-specific and global conversation information. After receiving the initial conversation information, clients maintain a conversation state, which is used in updating clients from a web service store through a conversation synchronization command employing an internal application programming interface within the email service.

公开(公告)号：US20110227639A1

公开(公告)日：2011-09-22

申请号：US12727833

申请日：2010-03-19

申请人： Michael ThaiThanh Phan ,  Chiaming Chai ,  Manish Garg

发明人： Michael ThaiThanh Phan ,  Chiaming Chai ,  Manish Garg

IPC分类号： G06G7/00 ,  H03F3/45

CPC分类号： G11C7/02 ,  G11C7/065

摘要： A sense amplifier circuit is implemented for suppressing Miller effect capacitive coupling. The amplifier circuit comprises a differential amplifier circuit having a first input, a first output interstitial node, a second input, a second output interstitial node, a third input to enable or disable the differential amplifier, and having an equalizer circuit coupled between the first output interstitial node and the second output interstitial node. The amplifier circuit also comprises a cross coupled latch circuit having a first latch input coupled to the first output interstitial node, a second latch input coupled to the second output interstitial node, a first latch output, and a second latch output, wherein during a first time period the first latch output and the second latch output are precharged, the differential amplifier circuit is disabled, and the equalizer circuit is enabled to suppress the Miller effect capacitive coupling on the sense amplifier inputs.

摘要翻译： 实现了一种用于抑制米勒效应电容耦合的读出放大器电路。 所述放大器电路包括差分放大器电路，所述差分放大器电路具有第一输入端，第一输出间隙节点，第二输入端，第二输出间隙型节点，第三输入端，用于使能或禁止差分放大器，以及具有耦合在第一输出端 间质性节点和第二输出间质性节点。 放大器电路还包括交叉耦合的锁存电路，其具有耦合到第一输出间隙节点的第一锁存器输入，耦合到第二输出间隙节点的第二锁存器输入，第一锁存器输出和第二锁存器输出，其中在第一 第一锁存器输出和第二锁存器输出被预充电的时间段，差分放大器电路被禁止，并且均衡器电路被使能以抑制在感测放大器输入上的米勒效应电容耦合。

公开(公告)号：US08008961B2

公开(公告)日：2011-08-30

申请号：US12637321

申请日：2009-12-14

申请人： Manish Garg ,  Chiaming Chai ,  Jeffrey Todd Bridges

发明人： Manish Garg ,  Chiaming Chai ,  Jeffrey Todd Bridges

IPC分类号： H03K3/00

CPC分类号： H03K3/0315 ,  H03K2005/00058 ,  H03K2005/00215

摘要： Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s).

摘要翻译： 公开了可用于生成用于功能电路的时钟信号以避免或降低性能裕度的自适应时钟发生器，系统和相关方法。 在某些实施例中，时钟发生器根据在与功能电路中所选择的延迟路径相关的延迟电路中提供的延迟路径来自主地且自适应地生成时钟信号。 时钟发生器包括适于接收输入信号并将输入信号延迟与功能电路的延迟路径相关的量以产生输出信号的延迟电路。 反馈电路耦合到延迟电路并响应于输出信号，其中反馈电路适于在振荡环路配置中产生回到延迟电路的输入信号。 输入信号可用于向功能电路提供时钟信号。

公开(公告)号：US20060168463A1

公开(公告)日：2006-07-27

申请号：US10561627

申请日：2003-12-03

申请人： Andrei Terechko ,  Manish Garg

发明人： Andrei Terechko ,  Manish Garg

IPC分类号： G06F1/30

CPC分类号： G06F9/30141 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3237 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/30083 ,  G06F9/3012 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/171

摘要： A circuit arrangement and method of controlling power dissipation utilize a register file (60) with power dissipation control capabilities through a banked register design coupled with enable logic (62, 82) that is configured to selectively disable unused banks (70) of registers by selectively gating off clock (74), address (76) and data (78) inputs supplied thereto.

摘要翻译： 一种控制功率消耗的电路装置和方法利用具有功率消耗控制能力的寄存器文件（60），该寄存器文件（60）具有耦合到使能逻辑（62,82）的组合寄存器设计，其被配置为通过选择性地禁用寄存器的未使用库（70） 选通提供给其的输入时钟（74），地址（76）和数据（78）。

公开(公告)号：US09294307B2

公开(公告)日：2016-03-22

申请号：US13267971

申请日：2011-10-07

申请人： Gautam Bhakar ,  Manish Garg

发明人： Gautam Bhakar ,  Manish Garg

IPC分类号： G06F15/16 ,  H04L12/58 ,  G06Q10/10

CPC分类号： H04L67/1095 ,  G06Q10/107 ,  H04L12/585 ,  H04L12/586 ,  H04L51/12 ,  H04L51/16 ,  H04L67/06

摘要： Systems and methods for synchronizing conversation data between a client and a server in a networked computing environment. A data structure associated with an e-mail conversation is encoded and shuttled between the client and the server. When received at the server, the data structure is analyzed to determine changes within the e-mail conversation. The data structure is subsequently modified to reflect or include only those changes to minimize the amount of information transferred between the server and client.

摘要翻译： 用于在联网计算环境中的客户端和服务器之间同步会话数据的系统和方法。 与电子邮件对话相关联的数据结构在客户端和服务器之间进行编码和穿梭。 当在服务器接收到数据结构时，分析数据结构以确定电子邮件对话内的变化。 随后修改数据结构以反映或仅包括这些更改，以最小化在服务器和客户端之间传输的信息量。

公开(公告)号：US08724373B2

公开(公告)日：2014-05-13

申请号：US13609520

申请日：2012-09-11

申请人： Manish Garg ,  Michael ThaiThanh Phan

发明人： Manish Garg ,  Michael ThaiThanh Phan

IPC分类号： G11C8/08 ,  G11C8/16 ,  G11C8/12 ,  G11C7/08 ,  G11C5/06 ,  G11C11/419 ,  G11C11/408

CPC分类号： G11C8/08 ,  G11C5/063 ,  G11C7/08 ,  G11C8/12 ,  G11C8/16 ,  G11C11/4085 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419

摘要： Systems and methods for selectively boosting word-line (WL) voltage in a memory cell array. The method relies several embodiments to minimize energy costs associated with WL boost scheme. One embodiment generates a transient voltage boost rather than supply a DC voltage boost. The transient boost generation may be controlled on a cycle basis and can be disabled when the array is not accessed. Another embodiment allows the system to generate the transient voltage boost locally, near a WL driver and only during the cycles when it is needed. Localized boost voltage generation reduces the load capacitance that needs to be boosted to higher voltage. Another embodiment efficiently distributes the transient boost to the WL drivers.

摘要翻译： 用于选择性地提高存储单元阵列中的字线（WL）电压的系统和方法。 该方法依赖于几个实施例来最小化与WL升压方案相关联的能量成本。 一个实施例产生瞬态升压而不是提供直流升压。 瞬态升压生成可以以循环为基础进行控制，并且可以在不访问阵列时禁用。 另一个实施例允许系统在WL驱动器附近本地产生瞬态电压升高，并且仅在需要时在周期期间产生。 本地化的升压电压降低了需要升压到更高电压的负载电容。 另一个实施例有效地将瞬态升压分配给WL驱动器。

公开(公告)号：US20100153954A1

公开(公告)日：2010-06-17

申请号：US12333063

申请日：2008-12-11

申请人： Michael William Morrow ,  Manish Garg

发明人： Michael William Morrow ,  Manish Garg

IPC分类号： G06F9/46

CPC分类号： G06F9/5094 ,  G06F1/329 ,  Y02D10/22 ,  Y02D10/24

摘要： Techniques for adaptive thread scheduling on a plurality of cores for reducing system energy are described. In one embodiment, a thread scheduler receives leakage current information associated with the plurality of cores. The leakage current information is employed to schedule a thread on one of the plurality of cores to reduce system energy usage. On chip calibration of the sensors is also described.

摘要翻译： 描述了用于减少系统能量的用于多个核上的自适应线程调度的技术。 在一个实施例中，线程调度器接收与多个核相关联的漏电流信息。 泄漏电流信息用于在多个核心之一上调度线程以减少系统能量消耗。 还描述了传感器的片上校准。

公开(公告)号：US07725792B2

公开(公告)日：2010-05-25

申请号：US11365716

申请日：2006-03-01

申请人： Manish Garg ,  Fadi Adel Hamdan

发明人： Manish Garg ,  Fadi Adel Hamdan

IPC分类号： G01R31/28

CPC分类号： G01R31/318541 ,  G01R31/318572 ,  G11C29/1201 ,  G11C29/32

摘要： A dual-path, multimode sequential storage element (SSE) is described herein. In one example, the dual-path, multimode SSE comprises first and second sequential storage elements, a data input, a data output, and a selector mechanism. The first and second sequential storage elements each have an input and an output. The data input is coupled to the inputs of both sequential storage elements and is configured to accept data. The data output is coupled to the outputs of both sequential storage elements and is configured to output the data. The selector mechanism is configured to select one of the sequential storage elements for passing the data from the data input to the data output. In one example, the first sequential storage element comprises a pulse-triggered storage element and the second sequential storage element comprises a master-slave storage element.

摘要翻译： 本文描述了双路径多模式顺序存储元件（SSE）。 在一个示例中，双路多模SSE包括第一和第二顺序存储元件，数据输入，数据输出和选择器机构。 第一和第二顺序存储元件各自具有输入和输出。 数据输入耦合到两个顺序存储元件的输入，并被配置为接受数据。 数据输出耦合到两个顺序存储元件的输出，并被配置为输出数据。 选择器机构被配置为选择用于将数据从数据输入传送到数据输出的顺序存储元件之一。 在一个示例中，第一顺序存储元件包括脉冲触发存储元件，并且第二顺序存储元件包括主从存储元件。