公开(公告)号：US08488403B2

公开(公告)日：2013-07-16

申请号：US12757033

申请日：2010-04-08

Applicant: Manoj Sachdev ,  Mohammad Sharifkhani ,  Jaspal Singh Shah ,  David Rennie

Inventor： Manoj Sachdev ,  Mohammad Sharifkhani ,  Jaspal Singh Shah ,  David Rennie

IPC: G11C7/02

CPC classification number: G11C7/062 ,  G11C2207/063 ,  G11C2207/104

Abstract: An offset cancellation scheme for sense amplification is described. The scheme consists of group of transistors which are selectively coupled to high and low voltage levels via multi-phase timing. This results in a voltage level on sensing nodes of interest which are a function of transistor mismatch. The resulting voltage levels act to compensates for the transistor mismatch, thereby improving the reliability of the sense amplifier in the presence of process non-idealities. The offset cancellation scheme is applicable to numerous types of sense amplifiers, amplifiers, and comparators.

Abstract translation: 描述了用于感测放大的偏移消除方案。 该方案由通过多相定时选择性地耦合到高电压和低电压电平的晶体管组成。 这导致感兴趣的感测节点上的电压电平，其是晶体管不匹配的函数。 所产生的电压电平用于补偿晶体管失配，从而在存在工艺非理想性的情况下提高读出放大器的可靠性。 偏移消除方案适用于许多类型的读出放大器，放大器和比较器。

公开(公告)号：US08072797B2

公开(公告)日：2011-12-06

申请号：US12494908

申请日：2009-06-30

Applicant: Manoj Sachdev ,  David Rennie

Inventor： Manoj Sachdev ,  David Rennie

IPC: G11C11/00

CPC classification number: G11C11/412

Abstract: A Static Random Access Memory (SRAM) cell without dedicated access transistors is described. The SRAM cell comprises a plurality of transistors configured to provide at least a pair of storage nodes for storing complementary logic values represented by corresponding voltages. The transistors comprise at least one bitline transistor, at least on wordline transistor and at least two supply transistors. The bitline transistor is configured to selectively couple one of the storage nodes to at least one corresponding bitline, the bitline for being shared by SRAM cells in one of a common row or column. The wordline transistor is configured to selectively couple another of the storage nodes to at least one corresponding wordline, the wordline for being shared by SRAM cells in the other of the common row or column. The supply transistors are configured to selectively couple corresponding ones of the storage nodes to a supply voltage.

Abstract translation: 描述了没有专用存取晶体管的静态随机存取存储器（SRAM）单元。 SRAM单元包括多个晶体管，其被配置为提供至少一对存储节点，用于存储由对应电压表示的互补逻辑值。 晶体管至少在字线晶体管和至少两个电源晶体管上包括至少一个位线晶体管。 位线晶体管被配置为选择性地将存储节点之一耦合到至少一个相应的位线，该位线用于由公共行或列之一中的SRAM单元共享的位线。 字线晶体管被配置为选择性地将另一个存储节点耦合到至少一个相应的字线，该字线由公共行或列中的另一个中的SRAM单元共享。 电源晶体管被配置为选择性地将相应的存储节点耦合到电源电压。

公开(公告)号：US20110255359A1

公开(公告)日：2011-10-20

申请号：US12757033

申请日：2010-04-08

Applicant: Manoj Sachdev ,  Mohammad Sharifkhani ,  Jaspal Singh Shah ,  David Rennie

Inventor： Manoj Sachdev ,  Mohammad Sharifkhani ,  Jaspal Singh Shah ,  David Rennie

IPC: G11C7/06 ,  H03F3/16

CPC classification number: G11C7/062 ,  G11C2207/063 ,  G11C2207/104

Abstract: An offset cancellation scheme for sense amplification is described. The scheme consists of group of transistors which are selectively coupled to high and low voltage levels via multi-phase timing. This results in a voltage level on nodes of interest which are a function of transistor mismatch. The resulting voltage levels act to compensates for the transistor mismatch, thereby improving the reliability of the sense amplifier in the presence of process non-idealities. The offset cancellation scheme is applicable to numerous types of sense amplifiers.

Abstract translation: 描述了用于感测放大的偏移消除方案。 该方案由通过多相定时选择性地耦合到高电压和低电压电平的晶体管组成。 这导致感兴趣的节点上的电压电平是晶体管不匹配的函数。 所产生的电压电平用于补偿晶体管失配，从而在存在工艺非理想性的情况下提高读出放大器的可靠性。 偏移消除方案适用于多种类型的读出放大器。

公开(公告)号：US20100110773A1

公开(公告)日：2010-05-06

申请号：US12494908

申请日：2009-06-30

Applicant: Manoj Sachdev ,  David Rennie

Inventor： Manoj Sachdev ,  David Rennie

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C11/412

Abstract: A Static Random Access Memory (SRAM) cell without dedicated access transistors is described. The SRAM cell comprises a plurality of transistors configured to provide at least a pair of storage nodes for storing complementary logic values represented by corresponding voltages. The transistors comprise at least one bitline transistor, at least on wordline transistor and at least two supply transistors. The bitline transistor is configured to selectively couple one of the storage nodes to at least one corresponding bitline, the bitline for being shared by SRAM cells in one of a common row or column. The wordline transistor is configured to selectively couple another of the storage nodes to at least one corresponding wordline, the wordline for being shared by SRAM cells in the other of the common row or column. The supply transistors are configured to selectively couple corresponding ones of the storage nodes to a supply voltage.

Abstract translation: 描述了没有专用存取晶体管的静态随机存取存储器（SRAM）单元。 SRAM单元包括多个晶体管，其被配置为提供至少一对存储节点，用于存储由对应电压表示的互补逻辑值。 晶体管至少在字线晶体管和至少两个电源晶体管上包括至少一个位线晶体管。 位线晶体管被配置为选择性地将存储节点之一耦合到至少一个相应的位线，该位线用于由公共行或列之一中的SRAM单元共享的位线。 字线晶体管被配置为选择性地将另一个存储节点耦合到至少一个相应的字线，该字线由公共行或列中的另一个中的SRAM单元共享。 电源晶体管被配置为选择性地将相应的存储节点耦合到电源电压。

公开(公告)号：US20130265819A1

公开(公告)日：2013-10-10

申请号：US13751763

申请日：2013-01-28

Applicant: David Rennie ,  Manoj Sachdev

Inventor： David Rennie ,  Manoj Sachdev

IPC: G11C11/412

CPC classification number: G11C11/412 ,  G11C11/4125 ,  H03K19/007

Abstract: A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes. The outer storage nodes act to limit feedback between the core storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the core storage nodes act to limit feedback between the outer storage nodes with the same effect. This cell has advantages compared with other robust storage cells in that there are only two paths between the supply voltage and ground which limits the leakage power. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell.

Abstract translation: 存储单元具有对软错误的改进的鲁棒性。 存储单元包括互补的核心存储节点和互补的外部存储节点。 外部存储节点用于限制核心存储节点之间的反馈，并且能够在发生软错误的情况下恢复核心存储节点的逻辑状态。 类似地，核心存储节点用于限制具有相同效果的外部存储节点之间的反馈。 与其他强大的存储单元相比，该单元具有优点，因为在电源电压和地之间只有两条路径限制漏电功率。 利用所提出的存储单元的SRAM单元可以通过配置成将互补存储节点选择性地耦合到相应位线的两个存取晶体管来实现。 可以使用选择性地将数据耦合到所提出的存储单元中的各种传输门来实现触发器。

公开(公告)号：US08363455B2

公开(公告)日：2013-01-29

申请号：US12630947

申请日：2009-12-04

Applicant: David Rennie ,  Manoj Sachdev

Inventor： David Rennie ,  Manoj Sachdev

IPC: G11C11/00

CPC classification number: G11C11/412 ,  G11C11/4125 ,  H03K19/007

Abstract: A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes. The outer storage nodes act to limit feedback between the core storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the core storage nodes act to limit feedback between the outer storage nodes with the same effect. This cell has advantages compared with other robust storage cells in that there are only two paths between the supply voltage and ground which limits the leakage power. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell.

Abstract translation: 存储单元具有对软错误的改进的鲁棒性。 存储单元包括互补的核心存储节点和互补的外部存储节点。 外部存储节点用于限制核心存储节点之间的反馈，并且能够在发生软错误的情况下恢复核心存储节点的逻辑状态。 类似地，核心存储节点用于限制具有相同效果的外部存储节点之间的反馈。 与其他强大的存储单元相比，该单元具有优点，因为在电源电压和地之间只有两条路径限制漏电功率。 利用所提出的存储单元的SRAM单元可以通过配置成将互补存储节点选择性地耦合到相应位线的两个存取晶体管来实现。 可以使用选择性地将数据耦合到所提出的存储单元中的各种传输门来实现触发器。

公开(公告)号：US08164943B2

公开(公告)日：2012-04-24

申请号：US12749857

申请日：2010-03-30

Applicant: Manoj Sachdev ,  David Rennie

Inventor： Manoj Sachdev ,  David Rennie

IPC: G11C11/00

CPC classification number: G11C11/4125 ,  G11C11/413 ,  H03K3/356165 ,  H03K3/356182

Abstract: A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary lower storage nodes and complementary upper storage nodes. The upper storage nodes act to limit feedback between the lower storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the lower storage nodes act to limit feedback between the upper storage nodes with the same effect. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell.

Abstract translation: 存储单元具有对软错误的改进的鲁棒性。 存储单元包括互补的下部存储节点和互补的上部存储节点。 上部存储节点用于限制下层存储节点之间的反馈，并且能够在发生软错误的情况下恢复核心存储节点的逻辑状态。 类似地，较低的存储节点用于限制具有相同效果的上层存储节点之间的反馈。 利用所提出的存储单元的SRAM单元可以通过配置成将互补存储节点选择性地耦合到相应位线的两个存取晶体管来实现。 可以使用选择性地将数据耦合到所提出的存储单元中的各种传输门来实现触发器。

公开(公告)号：US20110298496A1

公开(公告)日：2011-12-08

申请号：US13151276

申请日：2011-06-02

Applicant: David Rennie ,  Manoj Sachdev

Inventor： David Rennie ,  Manoj Sachdev

IPC: H03F3/45

CPC classification number: G11C7/065 ,  G11C11/413

Abstract: A sense amplifier for use in a memory array having a plurality of memory cells is provided. The sense amplifier provides low power dissipation, rapid sensing and high yield sensing operation. The inputs to the sense amplifier are the differential bitlines of an SRAM column, which are coupled to the sense amplifier via the sources of two PMOS transistors. A CMOS latching element comprised of two NMOS transistors and the aforementioned PMOS transistors act to amplify any difference between the differential bitline voltages and resolve the output nodes of the sense amplifier to a full swing value. The latching element is gated with two additional PMOS transistors which act to block the latching operation until the sense amplifier is enabled. One or more equalization transistors ensure the latch remains in the metastable state until it is enabled. Once the latch has resolved it consumes no DC power, aside from leakage.

Abstract translation: 提供了一种用于具有多个存储单元的存储器阵列中的读出放大器。 感测放大器提供低功耗，快速感测和高产量感测操作。 读出放大器的输入是SRAM列的差分位线，它们通过两个PMOS晶体管的源极耦合到读出放大器。 由两个NMOS晶体管和上述PMOS晶体管组成的CMOS锁存元件用于放大差分位线电压之间的任何差异，并将读出放大器的输出节点解析为全摆幅值。 闭锁元件门控有两个附加的PMOS晶体管，其用于阻止锁存操作，直到读出放大器被使能。 一个或多个均衡晶体管确保闩锁保持在亚稳态，直到其被使能。 一旦闩锁已经解决，除了泄漏外，它不会消耗直流电。

公开(公告)号：US20100246242A1

公开(公告)日：2010-09-30

申请号：US12749857

申请日：2010-03-30

Applicant: Manoj Sachdev ,  David Rennie

Inventor： Manoj Sachdev ,  David Rennie

IPC: G11C11/00 ,  H03K19/173

CPC classification number: G11C11/4125 ,  G11C11/413 ,  H03K3/356165 ,  H03K3/356182

Abstract: A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary lower storage nodes and complementary upper storage nodes. The upper storage nodes act to limit feedback between the lower storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the lower storage nodes act to limit feedback between the upper storage nodes with the same effect. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell.

Abstract translation: 存储单元具有对软错误的改进的鲁棒性。 存储单元包括互补的下部存储节点和互补的上部存储节点。 上部存储节点用于限制下层存储节点之间的反馈，并且能够在发生软错误的情况下恢复核心存储节点的逻辑状态。 类似地，较低的存储节点用于限制具有相同效果的上层存储节点之间的反馈。 利用所提出的存储单元的SRAM单元可以通过配置成将互补存储节点选择性地耦合到相应位线的两个存取晶体管来实现。 可以使用选择性地将数据耦合到所提出的存储单元中的各种传输门来实现触发器。

公开(公告)号：US20100195374A1

公开(公告)日：2010-08-05

申请号：US12630947

申请日：2009-12-04

Applicant: David Rennie ,  Manoj Sachdev

Inventor： David Rennie ,  Manoj Sachdev

IPC: G11C11/00 ,  H03K19/173

CPC classification number: G11C11/412 ,  G11C11/4125 ,  H03K19/007

Abstract: A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes. The outer storage nodes act to limit feedback between the core storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the core storage nodes act to limit feedback between the outer storage nodes with the same effect. This cell has advantages compared with other robust storage cells in that there are only two paths between the supply voltage and ground which limits the leakage power. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell.

Abstract translation: 存储单元具有对软错误的改进的鲁棒性。 存储单元包括互补的核心存储节点和互补的外部存储节点。 外部存储节点用于限制核心存储节点之间的反馈，并且能够在发生软错误的情况下恢复核心存储节点的逻辑状态。 类似地，核心存储节点用于限制具有相同效果的外部存储节点之间的反馈。 与其他强大的存储单元相比，该单元具有优点，因为在电源电压和地之间只有两条路径限制漏电功率。 利用所提出的存储单元的SRAM单元可以通过配置成将互补存储节点选择性地耦合到相应位线的两个存取晶体管来实现。 可以使用选择性地将数据耦合到所提出的存储单元中的各种传输门来实现触发器。