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1.发明授权Sense-amplification with offset cancellation for static random access memories 有权用于静态随机存取存储器的偏移消除的感测放大公开(公告)号：US08488403B2
公开(公告)日：2013-07-16
申请号：US12757033
申请日：2010-04-08
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C2207/063 , G11C2207/104
摘要： An offset cancellation scheme for sense amplification is described. The scheme consists of group of transistors which are selectively coupled to high and low voltage levels via multi-phase timing. This results in a voltage level on sensing nodes of interest which are a function of transistor mismatch. The resulting voltage levels act to compensates for the transistor mismatch, thereby improving the reliability of the sense amplifier in the presence of process non-idealities. The offset cancellation scheme is applicable to numerous types of sense amplifiers, amplifiers, and comparators.
摘要翻译： 描述了用于感测放大的偏移消除方案。 该方案由通过多相定时选择性地耦合到高电压和低电压电平的晶体管组成。 这导致感兴趣的感测节点上的电压电平，其是晶体管不匹配的函数。 所产生的电压电平用于补偿晶体管失配，从而在存在工艺非理想性的情况下提高读出放大器的可靠性。 偏移消除方案适用于许多类型的读出放大器，放大器和比较器。
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2.发明申请Sense-Amplification With Offset Cancellation For Static Random Access Memories 有权用于静态随机存取存储器的偏移消除的感测放大公开(公告)号：US20110255359A1
公开(公告)日：2011-10-20
申请号：US12757033
申请日：2010-04-08
CPC分类号： G11C7/062 , G11C2207/063 , G11C2207/104
摘要： An offset cancellation scheme for sense amplification is described. The scheme consists of group of transistors which are selectively coupled to high and low voltage levels via multi-phase timing. This results in a voltage level on nodes of interest which are a function of transistor mismatch. The resulting voltage levels act to compensates for the transistor mismatch, thereby improving the reliability of the sense amplifier in the presence of process non-idealities. The offset cancellation scheme is applicable to numerous types of sense amplifiers.
摘要翻译： 描述了用于感测放大的偏移消除方案。 该方案由通过多相定时选择性地耦合到高电压和低电压电平的晶体管组成。 这导致感兴趣的节点上的电压电平是晶体管不匹配的函数。 所产生的电压电平用于补偿晶体管失配，从而在存在工艺非理想性的情况下提高读出放大器的可靠性。 偏移消除方案适用于多种类型的读出放大器。
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3.发明授权Threshold voltage mismatch compensation sense-amplifiers for static random access memories with multiple differential inputs 有权具有多个差分输入的静态随机存取存储器的阈值电压失配补偿读出放大器公开(公告)号：US09542995B2
公开(公告)日：2017-01-10
申请号：US14470866
申请日：2014-08-27
申请人： Manoj Sachdev , Jaspal Singh Shah
发明人： Manoj Sachdev , Jaspal Singh Shah
IPC分类号： G11C11/419
CPC分类号： G11C11/419
摘要： Sense amplifier configurations for memories are described. In these configurations, the differential inputs are boosted proportional to the respective bitline voltage enabling a low-voltage, reliable, faster sense amplifier operation. Disclosed sense amplifiers are also capable of compensating the threshold mismatch between the sensing transistors.
摘要翻译： 描述用于存储器的感测放大器配置。 在这些配置中，差分输入与相应的位线电压成正比，从而能够实现低电压，可靠，更快的读出放大器操作。 公开的读出放大器还能够补偿感测晶体管之间的阈值失配。
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4.发明申请THRESHOLD VOLTAGE MISMATCH COMPENSATION SENSE-AMPLIFIERS FOR STATIC RANDOM ACCESS MEMORIES WITH MULTIPLE DIFFERENTIAL INPUTS 审中-公开用于具有多种差分输入的静态随机存取存储器的阈值电压误差补偿公开(公告)号：US20160203856A1
公开(公告)日：2016-07-14
申请号：US14470866
申请日：2014-08-27
申请人： Manoj Sachdev , Jaspal Singh Shah
发明人： Manoj Sachdev , Jaspal Singh Shah
IPC分类号： G11C11/419
CPC分类号： G11C11/419
摘要： Sense amplifier configurations for memories are described. In these configurations, the differential inputs are boosted proportional to the respective bitline voltage enabling a low-voltage, reliable, faster sense amplifier operation. Disclosed sense amplifiers are also capable of compensating the threshold mismatch between the sensing transistors.
摘要翻译： 描述用于存储器的感测放大器配置。 在这些配置中，差分输入与相应的位线电压成正比，从而能够实现低电压，可靠，更快的读出放大器操作。 公开的读出放大器还能够补偿感测晶体管之间的阈值失配。
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公开(公告)号：US07643329B2
公开(公告)日：2010-01-05
申请号：US11621679
申请日：2007-01-10
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： An asymmetric Static Random Access Memory (SRAM) cell is provided. The SRAM cell comprises first and second storage nodes, drive transistors and access transistors. The first and second storage nodes are configured to store complementary voltages. The drive transistors are configured to selectively couple each of the first and second storage nodes to corresponding high and low voltage power supplies, and maintain a first logic state through a feedback loop. The access transistors are configured to selectively couple each of the first and second storage nodes to corresponding first and second bit-lines and maintain a second logic state through relative transistor leakage currents. A method for reading from and writing to the SRAM cell are also provided.
摘要翻译： 提供了非对称静态随机存取存储器（SRAM）单元。 SRAM单元包括第一和第二存储节点，驱动晶体管和存取晶体管。 第一和第二存储节点被配置为存储互补电压。 驱动晶体管被配置为选择性地将第一和第二存储节点中的每一个耦合到相应的高电压和低电压电源，并且通过反馈回路保持第一逻辑状态。 存取晶体管被配置为选择性地将第一和第二存储节点中的每一个耦合到相应的第一和第二位线，并通过相对晶体管漏电流维持第二逻辑状态。 还提供了用于从SRAM单元读取和写入SRAM单元的方法。
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6.发明授权Segmented column virtual ground scheme in a static random access memory (SRAM) circuit 失效静态随机存取存储器（SRAM）电路中的分段列虚拟接地方案公开(公告)号：US07372721B2
公开(公告)日：2008-05-13
申请号：US11552655
申请日：2006-10-25
IPC分类号： G11C7/00
CPC分类号： G11C11/413 , G11C8/10 , G11C8/12 , G11C11/412
摘要： A static random access memory (SRAM) cell array is provided that reduces leakage current. The SRAM cell array is configured in a plurality of columns. Each of the columns comprises: a column virtual ground node; a column switch for selectively coupling the column virtual ground node to one of a ground or a nominal low voltage; and a plurality of segments. Each of the segments comprises: a segment virtual ground node; a plurality of SRAM cells including a virtual ground signal coupled to the segment virtual ground node; and a virtual ground switch for selectively coupling the segment virtual ground node to one of either a nominal low voltage or the column virtual ground node. A method for operating the SRAM cell array is also described.
摘要翻译： 提供了一种减少漏电流的静态随机存取存储器（SRAM）单元阵列。 SRAM单元阵列被配置成多列。 每列包括：虚拟虚拟接地节点; 用于选择性地将列虚拟接地节点耦合到接地或标称低电压之一的列开关; 和多个段。 每个段包括：段虚拟接地节点; 多个SRAM单元，包括耦合到所述段虚拟接地节点的虚拟接地信号; 以及用于选择性地将段虚拟接地节点耦合到标称低电压或列虚拟接地节点之一的虚拟接地开关。 还描述了用于操作SRAM单元阵列的方法。
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公开(公告)号：US20070177419A1
公开(公告)日：2007-08-02
申请号：US11621679
申请日：2007-01-10
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： An asymmetric Static Random Access Memory (SRAM) cell is provided. The SRAM cell comprises first and second storage nodes, drive transistors and access transistors. The first and second storage nodes are configured to store complementary voltages. The drive transistors are configured to selectively couple each of the first and second storage nodes to corresponding high and low voltage power supplies, and maintain a first logic state through a feedback loop. The access transistors are configured to selectively couple each of the first and second storage nodes to corresponding first and second bit-lines and maintain a second logic state through relative transistor leakage currents. A method for reading from and writing to the SRAM cell are also provided.
摘要翻译： 提供了非对称静态随机存取存储器（SRAM）单元。 SRAM单元包括第一和第二存储节点，驱动晶体管和存取晶体管。 第一和第二存储节点被配置为存储互补电压。 驱动晶体管被配置为选择性地将第一和第二存储节点中的每一个耦合到相应的高电压和低电压电源，并且通过反馈回路保持第一逻辑状态。 存取晶体管被配置为选择性地将第一和第二存储节点中的每一个耦合到相应的第一和第二位线，并通过相对晶体管漏电流维持第二逻辑状态。 还提供了用于从SRAM单元读取和写入SRAM单元的方法。
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8.发明申请Segmented Column Virtual Ground Scheme In A Static Random Access Memory (SRAM) Circuit 失效静态随机存取存储器（SRAM）电路中的分段列虚拟接地方案公开(公告)号：US20070217262A1
公开(公告)日：2007-09-20
申请号：US11552655
申请日：2006-10-25
IPC分类号： G11C16/04
CPC分类号： G11C11/413 , G11C8/10 , G11C8/12 , G11C11/412
摘要： A static random access memory (SRAM) cell array is provided that reduces leakage current. The SRAM cell array is configured in a plurality of columns. Each of the columns comprises: a column virtual ground node; a column switch for selectively coupling the column virtual ground node to one of a ground or a nominal low voltage; and a plurality of segments. Each of the segments comprises: a segment virtual ground node; a plurality of SRAM cells including a virtual ground signal coupled to the segment virtual ground node; and a virtual ground switch for selectively coupling the segment virtual ground node to one of either a nominal low voltage or the column virtual ground node. A method for operating the SRAM cell array is also described.
摘要翻译： 提供了一种减少漏电流的静态随机存取存储器（SRAM）单元阵列。 SRAM单元阵列被配置成多列。 每列包括：虚拟虚拟接地节点; 用于选择性地将列虚拟接地节点耦合到接地或标称低电压之一的列开关; 和多个段。 每个段包括：段虚拟接地节点; 多个SRAM单元，包括耦合到所述段虚拟接地节点的虚拟接地信号; 以及用于选择性地将段虚拟接地节点耦合到标称低电压或列虚拟接地节点之一的虚拟接地开关。 还描述了用于操作SRAM单元阵列的方法。
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公开(公告)号：US08072797B2
公开(公告)日：2011-12-06
申请号：US12494908
申请日：2009-06-30
申请人： Manoj Sachdev , David Rennie
发明人： Manoj Sachdev , David Rennie
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A Static Random Access Memory (SRAM) cell without dedicated access transistors is described. The SRAM cell comprises a plurality of transistors configured to provide at least a pair of storage nodes for storing complementary logic values represented by corresponding voltages. The transistors comprise at least one bitline transistor, at least on wordline transistor and at least two supply transistors. The bitline transistor is configured to selectively couple one of the storage nodes to at least one corresponding bitline, the bitline for being shared by SRAM cells in one of a common row or column. The wordline transistor is configured to selectively couple another of the storage nodes to at least one corresponding wordline, the wordline for being shared by SRAM cells in the other of the common row or column. The supply transistors are configured to selectively couple corresponding ones of the storage nodes to a supply voltage.
摘要翻译： 描述了没有专用存取晶体管的静态随机存取存储器（SRAM）单元。 SRAM单元包括多个晶体管，其被配置为提供至少一对存储节点，用于存储由对应电压表示的互补逻辑值。 晶体管至少在字线晶体管和至少两个电源晶体管上包括至少一个位线晶体管。 位线晶体管被配置为选择性地将存储节点之一耦合到至少一个相应的位线，该位线用于由公共行或列之一中的SRAM单元共享的位线。 字线晶体管被配置为选择性地将另一个存储节点耦合到至少一个相应的字线，该字线由公共行或列中的另一个中的SRAM单元共享。 电源晶体管被配置为选择性地将相应的存储节点耦合到电源电压。
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公开(公告)号：US20100110773A1
公开(公告)日：2010-05-06
申请号：US12494908
申请日：2009-06-30
申请人： Manoj Sachdev , David Rennie
发明人： Manoj Sachdev , David Rennie
CPC分类号： G11C11/412
摘要： A Static Random Access Memory (SRAM) cell without dedicated access transistors is described. The SRAM cell comprises a plurality of transistors configured to provide at least a pair of storage nodes for storing complementary logic values represented by corresponding voltages. The transistors comprise at least one bitline transistor, at least on wordline transistor and at least two supply transistors. The bitline transistor is configured to selectively couple one of the storage nodes to at least one corresponding bitline, the bitline for being shared by SRAM cells in one of a common row or column. The wordline transistor is configured to selectively couple another of the storage nodes to at least one corresponding wordline, the wordline for being shared by SRAM cells in the other of the common row or column. The supply transistors are configured to selectively couple corresponding ones of the storage nodes to a supply voltage.
摘要翻译： 描述了没有专用存取晶体管的静态随机存取存储器（SRAM）单元。 SRAM单元包括多个晶体管，其被配置为提供至少一对存储节点，用于存储由对应电压表示的互补逻辑值。 晶体管至少在字线晶体管和至少两个电源晶体管上包括至少一个位线晶体管。 位线晶体管被配置为选择性地将存储节点之一耦合到至少一个相应的位线，该位线用于由公共行或列之一中的SRAM单元共享的位线。 字线晶体管被配置为选择性地将另一个存储节点耦合到至少一个相应的字线，该字线由公共行或列中的另一个中的SRAM单元共享。 电源晶体管被配置为选择性地将相应的存储节点耦合到电源电压。
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