公开(公告)号：US08693256B2

公开(公告)日：2014-04-08

申请号：US12975055

申请日：2010-12-21

申请人： Marco Pasotti ,  Davide Lena ,  Fabio De Santis

发明人： Marco Pasotti ,  Davide Lena ,  Fabio De Santis

IPC分类号： G11C11/34

CPC分类号： G11C16/0433 ,  G11C16/0491 ,  G11C16/3418 ,  G11C2216/10

摘要： A non-volatile memory device integrated in a chip of semiconductor material. An embodiment of a memory device includes a plurality of memory cells. Each memory cell includes a first well and a second well of a first type of conductivity that are formed in an insulating region of a second type of conductivity. The memory cell further includes a first, a second, and a third region of the second type of conductivity that are formed in the first well; these regions define a selection transistor of MOS type and a storage transistor of floating gate MOS type that are coupled in series. Moreover, the memory device includes a selection gate of the selection transistor, a floating gate of the storage transistor, and a control gate of the storage transistor formed in the second well; the control gate is capacitively coupled with the floating gate.

摘要翻译： 集成在半导体材料芯片中的非易失性存储器件。 存储器件的实施例包括多个存储器单元。 每个存储单元包括形成在第二导电类型的绝缘区域中的第一导电类型的第一阱和第二阱。 存储单元还包括形成在第一阱中的第二类型导电性的第一，第二和第三区域; 这些区域限定了串联耦合的MOS型选择晶体管和浮置栅极MOS型存储晶体管。 此外，存储器件包括选择晶体管的选择栅极，存储晶体管的浮置栅极和形成在第二阱中的存储晶体管的控制栅极; 控制栅极与浮动栅极电容耦合。

公开(公告)号：US06894934B2

公开(公告)日：2005-05-17

申请号：US10728372

申请日：2003-12-04

申请人： Fabio De Santis ,  Marco Pasotti ,  Guido De Sandre

发明人： Fabio De Santis ,  Marco Pasotti ,  Guido De Sandre

IPC分类号： G11C7/06 ,  G11C11/56 ,  G11C16/28 ,  G11C7/00 ,  G11C16/06

CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C11/5642 ,  G11C16/28

摘要： A sensing circuit for a memory cell includes a first bias current generator connected between a first voltage reference and a first inner circuit node, and a second reference current generator connected to the first voltage reference. A comparator having a first input terminal is connected to a comparison circuit node that is connected to the second reference current generator, a second input terminal is connected to a circuit node that is connected to the first inner circuit node, and an output terminal forms an output terminal of the sensing circuit. A cascode-configured bias circuit is connected between the inner circuit node and a matching circuit node. The cascode-configured bias circuit is also connected to a second voltage reference. A current/voltage conversion stage is connected to the matching circuit node, to the comparison circuit node, and to a third voltage reference.

摘要翻译： 用于存储单元的感测电路包括连接在第一电压基准和第一内部电路节点之间的第一偏置电流发生器和连接到第一参考电压的第二参考电流发生器。 具有第一输入端子的比较器连接到连接到第二参考电流发生器的比较电路节点，第二输入端子连接到连接到第一内部电路节点的电路节点，并且输出端子形成 输出端子。 在内部电路节点和匹配电路节点之间连接共源共栅偏置电路。 共源共栅配置的偏置电路也连接到第二电压基准。 电流/电压转换级连接到匹配电路节点，连接到比较电路节点和第三参考电压。

公开(公告)号：US06535019B2

公开(公告)日：2003-03-18

申请号：US09989318

申请日：2001-11-20

申请人： Fabio De Santis

发明人： Fabio De Santis

IPC分类号： H03K190175

CPC分类号： H03K17/102 ,  H03K3/356113

摘要： A switching control method for level shifter includes a phase of de-selection of a high voltage value at an output terminal of the shifter using a selection signal. The de-selection phase may include starting the de-selection by bringing the selection signal to a low value; de-activating by way of the selection signal, the generation of a high-voltage signal being supplied to the shifter, and a reference voltage signal; computing the difference between an internal voltage signal of the shifter and the reference voltage signal; generating a control signal when the difference is found to be less than a threshold voltage value; and applying the selection signal to an input terminal of the shifter in the presence of the control signal.