公开(公告)号：US06894934B2

公开(公告)日：2005-05-17

申请号：US10728372

申请日：2003-12-04

申请人： Fabio De Santis ,  Marco Pasotti ,  Guido De Sandre

发明人： Fabio De Santis ,  Marco Pasotti ,  Guido De Sandre

IPC分类号： G11C7/06 ,  G11C11/56 ,  G11C16/28 ,  G11C7/00 ,  G11C16/06

CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C11/5642 ,  G11C16/28

摘要： A sensing circuit for a memory cell includes a first bias current generator connected between a first voltage reference and a first inner circuit node, and a second reference current generator connected to the first voltage reference. A comparator having a first input terminal is connected to a comparison circuit node that is connected to the second reference current generator, a second input terminal is connected to a circuit node that is connected to the first inner circuit node, and an output terminal forms an output terminal of the sensing circuit. A cascode-configured bias circuit is connected between the inner circuit node and a matching circuit node. The cascode-configured bias circuit is also connected to a second voltage reference. A current/voltage conversion stage is connected to the matching circuit node, to the comparison circuit node, and to a third voltage reference.

摘要翻译： 用于存储单元的感测电路包括连接在第一电压基准和第一内部电路节点之间的第一偏置电流发生器和连接到第一参考电压的第二参考电流发生器。 具有第一输入端子的比较器连接到连接到第二参考电流发生器的比较电路节点，第二输入端子连接到连接到第一内部电路节点的电路节点，并且输出端子形成 输出端子。 在内部电路节点和匹配电路节点之间连接共源共栅偏置电路。 共源共栅配置的偏置电路也连接到第二电压基准。 电流/电压转换级连接到匹配电路节点，连接到比较电路节点和第三参考电压。

公开(公告)号：US20060226873A1

公开(公告)日：2006-10-12

申请号：US11321732

申请日：2005-12-28

申请人： Guido De Sandre ,  Marco Poles ,  Marco Pasotti

发明人： Guido De Sandre ,  Marco Poles ,  Marco Pasotti

IPC分类号： H03K19/0175

CPC分类号： H03K19/018528 ,  H03K19/01707 ,  H03K19/01721

摘要： Level shifter translator of the type comprising at least one first transistor and one second MOS transistor belonging to respective circuit branches connected with a first common conduction terminal and connected towards a first potential reference and receiving, on the respective conduction terminals, input differential voltages, the first and the second transistor have respective circuit branches referring to a biasing circuit with current mirror, a third transistor allows to couple the second transistor to said biasing circuit, an inverter connected to an output of said the circuit with the output driving the third transistor.

公开(公告)号：US08264872B2

公开(公告)日：2012-09-11

申请号：US12548241

申请日：2009-08-26

申请人： Guido De Sandre ,  Marco Pasotti

发明人： Guido De Sandre ,  Marco Pasotti

IPC分类号： G11C11/00 ,  G11C8/10 ,  G11C7/00

CPC分类号： G11C13/0026 ,  G11C13/0004

摘要： A column decoder is for a phase-change memory device provided with an array of memory cells, a reading stage for reading data contained in the memory cells, and a programming stage for programming the data. The column decoder selects and enables biasing of a bitline of the array and generates a current path between the bitline and the reading stage or, alternatively, the programming stage, respectively during a reading or a programming operation of the contents of the memory cells. In the column decoder, a first decoder circuit generates a first current path between the bitline and the reading stage, and a second decoder circuit, distinct and separate from the first decoder circuit, generates a second current path, distinct from the first current path, between the bitline and the programming stage.

摘要翻译： 列解码器用于设置有存储器单元阵列的相变存储器件，用于读取存储单元中包含的数据的读取级和用于对数据进行编程的编程级。 列解码器选择并启用阵列的位线的偏置，并且在存储器单元的内容的读取或编程操作期间分别产生位线和读取级之间的电流路径，或者编程阶段。 在列解码器中，第一解码器电路在位线和读取级之间产生第一电流路径，并且与第一解码器电路不同且分离的第二解码器电路产生与第一电流路径不同的第二电流路径， 在位线和编程阶段之间。

公开(公告)号：US07504862B2

公开(公告)日：2009-03-17

申请号：US11321732

申请日：2005-12-28

申请人： Guido De Sandre ,  Marco Poles ,  Marco Pasotti

发明人： Guido De Sandre ,  Marco Poles ,  Marco Pasotti

IPC分类号： H03K19/0175

CPC分类号： H03K19/018528 ,  H03K19/01707 ,  H03K19/01721

摘要： Level shifter translator of the type comprising at least one first transistor and one second MOS transistor belonging to respective circuit branches connected with a first common conduction terminal and connected towards a first potential reference and receiving, on the respective conduction terminals, input differential voltages, the first and the second transistor have respective circuit branches referring to a biasing circuit with current mirror, a third transistor allows to couple the second transistor to said biasing circuit, an inverter connected to an output of said the circuit with the output driving the third transistor.

摘要翻译： 该类型的电平移位器转换器包括至少一个第一晶体管和一个第二MOS晶体管，属于与第一公共导通端子连接并连接到第一电位基准的相应电路分支，并且在相应的导通端子上接收输入差分电压， 第一晶体管和第二晶体管具有指向具有电流镜的偏置电路的各个电路分支，第三晶体管允许将第二晶体管耦合到所述偏置电路，反相器连接到所述电路的输出端，输出驱动第三晶体管。

公开(公告)号：US06687167B2

公开(公告)日：2004-02-03

申请号：US10225513

申请日：2002-08-20

申请人： Giovanni Guaitini ,  Marco Pasotti ,  Guido De Sandre ,  David Iezzi ,  Marco Poles ,  Pier Luigi Rolandi

发明人： Giovanni Guaitini ,  Marco Pasotti ,  Guido De Sandre ,  David Iezzi ,  Marco Poles ,  Pier Luigi Rolandi

IPC分类号： G11C1604

CPC分类号： G11C16/08 ,  G11C16/16

摘要： A non-volatile semiconductor memory device including an output connected to a row line and two supply terminals. Each elementary stage has an upper branch with a p-channel MOS transistor and a lower branch with an n-channel MOS transistor. In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor in the upper branch and a p-channel transistor in the lower branch. In this way it becomes possible to bias the elementary stages in such a manner the in the reading and programming phases the upper branch will function as pull-up and the lower branch as pull-down, while in the erasure phase the upper branch functions as pull-down and the lower branch as pull-up.

摘要翻译： 一种非易失性半导体存储器件，包括连接到行线和两个电源端子的输出。 每个基本级具有具有p沟道MOS晶体管的上部分支和具有n沟道MOS晶体管的下部分支。 为了允许逐行擦除存储器，而不必使用能够承受高电压的部件，每个基本级具有两个辅助MOS晶体管，即上部支路中的n沟道晶体管和 下分支。 以这种方式，可以以这种方式偏置基本级，在读取和编程阶段，上部分支将用作上拉和下部分支作为下拉，而在擦除阶段，上部分支作为 下拉和下部分支作为上拉。

公开(公告)号：US06687159B2

公开(公告)日：2004-02-03

申请号：US10036337

申请日：2001-12-19

申请人： Marco Pasotti ,  Giovanni Guaitini ,  Guido De Sandre ,  David Iezzi ,  Marco Poles ,  Pierluigi Rolandi

发明人： Marco Pasotti ,  Giovanni Guaitini ,  Guido De Sandre ,  David Iezzi ,  Marco Poles ,  Pierluigi Rolandi

IPC分类号： G11C1604

CPC分类号： G11C16/3481 ,  G11C8/08 ,  G11C16/12

摘要： A method of programming a plurality of memory cells are connected in parallel between first and second supply references and having their gate terminals connected together and, through row decoding means, also connected to an output terminal of an operational amplifier that is adapted to generate a word voltage signal, the first voltage reference being provided by a charge pump circuit. The programming method uses a program loop that includes the cells to be programmed and the operational amplifier, the charge pump circuit thus outputting a voltage ramp whose slope is a function of the cell demand. A programming circuit adapted to implement the method is also provided.

摘要翻译： 一种编程多个存储单元的方法并联连接在第一和第二供电基准之间，并且其栅极端子连接在一起，并且通过行解码装置也连接到适于产生字的运算放大器的输出端 电压信号，第一参考电压由电荷泵电路提供。 编程方法使用包括要编程的单元和运算放大器的程序循环，电荷泵电路因此输出其斜率是单元需求函数的电压斜坡。 还提供了一种适于实现该方法的编程电路。

公开(公告)号：US20100054031A1

公开(公告)日：2010-03-04

申请号：US12548241

申请日：2009-08-26

申请人： Guido De Sandre ,  Marco Pasotti

发明人： Guido De Sandre ,  Marco Pasotti

IPC分类号： G11C11/00 ,  G11C8/10 ,  G11C7/00

CPC分类号： G11C13/0026 ,  G11C13/0004

摘要： A column decoder is for a phase-change memory device provided with an array of memory cells, a reading stage for reading data contained in the memory cells, and a programming stage for programming the data. The column decoder selects and enables biasing of a bitline of the array and generates a current path between the bitline and the reading stage or, alternatively, the programming stage, respectively during a reading or a programming operation of the contents of the memory cells. In the column decoder, a first decoder circuit generates a first current path between the bitline and the reading stage, and a second decoder circuit, distinct and separate from the first decoder circuit, generates a second current path, distinct from the first current path, between the bitline and the programming stage.

摘要翻译： 列解码器用于设置有存储器单元阵列的相变存储器件，用于读取存储单元中包含的数据的读取级和用于对数据进行编程的编程级。 列解码器选择并启用阵列的位线的偏置，并且在存储器单元的内容的读取或编程操作期间分别产生位线和读取级之间的电流路径，或者编程阶段。 在列解码器中，第一解码器电路在位线和读取级之间产生第一电流路径，并且与第一解码器电路不同且分离的第二解码器电路产生与第一电流路径不同的第二电流路径， 在位线和编程阶段之间。

公开(公告)号：US07508716B2

公开(公告)日：2009-03-24

申请号：US10777457

申请日：2004-02-12

申请人： Marco Pasotti ,  Guido De Sandre ,  David Iezzi ,  Marco Poles

发明人： Marco Pasotti ,  Guido De Sandre ,  David Iezzi ,  Marco Poles

IPC分类号： G11C11/34 ,  G11C7/00

CPC分类号： G11C16/28 ,  G11C7/062 ,  G11C7/067 ,  G11C7/14

摘要： A sense amplifier for nonvolatile memory cells includes a reference cell, a first load, connected to the reference cell, and a second load, connectable to a nonvolatile memory cell, both the first load and the second load having controllable resistance; a control circuit of the first load and of the second load supplies the first load and the second load with a control voltage irrespective of an operating voltage between a first conduction terminal and a second conduction terminal of the first load.

摘要翻译： 用于非易失性存储单元的读出放大器包括参考单元，连接到参考单元的第一负载和可连接到非易失性存储单元的第二负载，第一负载和第二负载均具有可控电阻; 所述第一负载和所述第二负载的控制电路以与所述第一负载的第一导通端子和所述第二导通端子之间的工作电压无关的方式向所述第一负载和所述第二负载提供控制电压。

公开(公告)号：US06655758B2

公开(公告)日：2003-12-02

申请号：US10035909

申请日：2001-12-19

申请人： Marco Pasotti ,  Guido De Sandre ,  Giovanni Guaitini ,  David Iezzi ,  Marco Poles ,  PierLuigi Rolandi

发明人： Marco Pasotti ,  Guido De Sandre ,  Giovanni Guaitini ,  David Iezzi ,  Marco Poles ,  PierLuigi Rolandi

IPC分类号： G11C1604

CPC分类号： G11C16/34 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/28

摘要： Described herein is a method for storing a datum in a first and a second memory cells of a nonvolatile memory. The storage method envisages programming the first and second memory cells in a differential way, by setting a first threshold voltage in the first memory cell and a second threshold voltage different from the first threshold voltage in the second memory cell, the difference between the threshold voltages of the two memory cells representing a datum stored in the memory cells themselves.

公开(公告)号：US06622106B2

公开(公告)日：2003-09-16

申请号：US09833754

申请日：2001-04-11

申请人： Alessandro Rocchi ,  Marco Bisio ,  Guido De Sandre ,  Giovanni Guaitini ,  Marco Pasotti ,  Pier Luigi Rolandi

发明人： Alessandro Rocchi ,  Marco Bisio ,  Guido De Sandre ,  Giovanni Guaitini ,  Marco Pasotti ,  Pier Luigi Rolandi

IPC分类号： H03B500

CPC分类号： G01R31/2824

摘要： A digital device for testing and calibrating the oscillation frequency of an integrated oscillator circuit, the testing and calibrating device has as input at least first and second control parameters corresponding to limiting values of a predetermined range of values of the oscillation frequency sought for the integrated oscillator circuit, and it includes a comparison circuit for comparing a signal of known duration and a signal from the integrated oscillator circuit; a circuit connected to the comparison circuit, for generating calibration values for the signal from the integrated oscillator circuit; and a circuit for forcing storage of final calibration values of the signal from the integrated oscillator circuit into a storage and control section of the integrated oscillator circuit.

摘要翻译： 一种用于测试和校准集成振荡器电路的振荡频率的数字装置，所述测试和校准装置具有至少第一和第二控制参数，所述至少第一和第二控制参数对应于为集成振荡器寻找的振荡频率的预定值范围的极限值 并且其包括用于比较已知持续时间的信号和来自集成振荡器电路的信号的比较电路; 连接到比较电路的电路，用于产生来自集成振荡电路的信号的校准值; 以及用于强制将来自集成振荡器电路的信号的最终校准值存储到集成振荡器电路的存储和控制部分的电路。