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    Contact plug forming method
    1.
    发明授权
    Contact plug forming method 失效
    接触塞形成方法

    公开(公告)号：US5607878A

    公开(公告)日：1997-03-04

    申请号：US526543

    申请日：1995-09-12

    申请人： Mari Otsuka ,  Tomonori Kitakura ,  Kenichi Otsuka ,  Kazuya Mori

    发明人： Mari Otsuka ,  Tomonori Kitakura ,  Kenichi Otsuka ,  Kazuya Mori

    IPC分类号： H01L21/768 ,  H01L21/28

    CPC分类号： H01L21/76879 ,  Y10S148/017

    摘要： An inter-level insulation film is formed on a first-level interconnection layer and part of the inter-level insulation film which lies on the first-level interconnection layer is etched to form a contact hole. After a natural oxidation film formed on the surface of part of the first-level interconnection layer which is exposed in the contact hole is removed, the resultant structure is exposed to a gas atmosphere containing halogen to purify the surface of the inter-level insulation film. After this, a contact plug is deposited and formed on the first-level interconnection layer which is exposed in the contact hole by the selective CVD method to fill in the contact hole. A second-level interconnection layer is formed on the inter-level insulation film and the first-level and second-level interconnection layers are electrically connected to each other via the contact plug.

    摘要翻译： 层间绝缘膜形成在一级互连层上，并且位于第一级互连层上的层间绝缘膜的一部分被蚀刻以形成接触孔。 在形成在暴露在接触孔中的一级互连层的部分表面上的自然氧化膜被除去之后，将所得结构暴露于含有卤素的气氛中，以净化层间绝缘膜的表面 。 之后，在通过选择性CVD法在接触孔中露出的第一层互连层上沉积并形成接触插塞以填充接触孔。 第二级互连层形成在层间绝缘膜上，并且第一级和第二级互连层经由接触插塞彼此电连接。

    Apparatus and method for manufacturing a semiconductor device having a multi-wiring layer structure
    2.
    发明授权
    Apparatus and method for manufacturing a semiconductor device having a multi-wiring layer structure 失效
    一种具有多层结构的半导体器件的制造方法

    公开(公告)号：US06180513B2

    公开(公告)日：2001-01-30

    申请号：US08910007

    申请日：1997-08-12

    申请人： Mari Otsuka ,  Kenichi Otsuka

    发明人： Mari Otsuka ,  Kenichi Otsuka

    IPC分类号： H01L214763

    CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/76879

    摘要： Disclosed are an apparatus and a method for manufacturing a semiconductor device. A Si wafer set within an L/UL chamber is transferred under the state of a high vacuum through a transfer chamber into a Ti chamber. The wafer is heated to at least 300° C. within the Ti chamber by a heating mechanism arranged within the Ti chamber. Then, a TiSix film is formed at a bottom portion of a contact hole by a plasma CVD method using an Ar gas supplied through a gas line as a carrier gas and a TiCl4 gas supplied through another gas line as a source gas, Ti in the source gas being self-aligned with Si in the wafer. The wafer having the TiSix film formed therein is transferred through the transfer chamber into a W chamber without being exposed to the air atmosphere. Within the W chamber, a W film is consecutively deposited by a selective CVD method on the TiSix film. The particular technique makes it possible to form the TiSix film of a high quality at a bottom portion of the contact hole even if the contact hole has a large aspect ratio.

    摘要翻译： 公开了一种用于制造半导体器件的装置和方法。 L / UL室内的Si晶片在高真空状态下通过转移室转移到Ti室中。 通过设置在Ti室内的加热机构将晶片加热至Ti室内至少300℃。 然后，通过等离子体CVD法，使用通过气体管线作为载气供给的Ar气体和通过另一气体管线作为源气体供给的TiCl 4气体，在接触孔的底部形成TiSix膜，Ti 源气体与晶片中的Si自对准。 其中形成有TiSix膜的晶片通过传送室转移到W室中而不暴露于空气气氛。 在W室内，通过选择性CVD法在TiSix膜上连续沉积W膜。 特别的技术使得即使接触孔具有大的纵横比，也可以在接触孔的底部形成高品质的TiSix膜。

    Method of manufacturing semiconductor device having a multilayer wiring
    3.
    发明授权
    Method of manufacturing semiconductor device having a multilayer wiring 失效
    具有多层布线的半导体器件的制造方法

    公开(公告)号：US5834367A

    公开(公告)日：1998-11-10

    申请号：US629944

    申请日：1996-04-12

    申请人： Mari Otsuka ,  Kenichi Otsuka

    发明人： Mari Otsuka ,  Kenichi Otsuka

    IPC分类号： H01L21/285 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L21/283

    CPC分类号： H01L23/5226 ,  H01L21/76838 ,  H01L21/76879 ,  H01L23/485 ,  H01L2924/0002

    摘要： In a method of manufacturing a semiconductor device having a multilayer wiring structure, it has at least two underlying layers having different etching conditions. Firstly, the native oxide film formed on one of the underlying layers, or a barrier metal layer, is etched out under etching conditions suitable for the barrier metal layer. Then, the surface of the barrier metal layer is capped with a plugging material having etching conditions similar to or substantially the same as those of the other one of the underlying layers, or a lower wiring layer. Subsequently, the native oxide film and the etching by-product formed on the lower wiring layer are etched out under etching conditions suitable for the lower wiring layer. Thereafter, contact holes for the two underlying layers are buried with a conductive substance to establish electric connection with their respective upper conductive layers. With the above described steps, the entire manufacturing process is significantly simplified and the time required for burying the contact holes is greatly reduced without remarkably increasing the contact resistance between the barrier metal layer and the lower wiring layer and the respective buried conductive substances.

    摘要翻译： 在制造具有多层布线结构的半导体器件的方法中，它具有至少两个具有不同蚀刻条件的下层。 首先，在适合于阻挡金属层的蚀刻条件下，蚀刻形成在其中一层或阻挡金属层上的自然氧化膜。 然后，用具有与另一个下层或下布线层类似或基本相同的蚀刻条件的封堵材料封盖阻挡金属层的表面。 随后，在适合于下布线层的蚀刻条件下，蚀刻在下布线层上形成的自然氧化膜和蚀刻副产物。 此后，用导电物质掩埋两个下层的接触孔，以与它们各自的上导电层建立电连接。 通过上述步骤，整个制造过程被显着简化，并且大大降低了掩埋接触孔所需的时间，而不显着增加阻挡金属层与下部布线层之间的接触电阻以及相应的掩埋导电物质。

    Semiconductor device and method of manufacturing the same
    6.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08053268B2

    公开(公告)日：2011-11-08

    申请号：US12259732

    申请日：2008-10-28

    申请人： Mari Otsuka ,  Hiroyuki Kamijiyo ,  Hideaki Harakawa

    发明人： Mari Otsuka ,  Hiroyuki Kamijiyo ,  Hideaki Harakawa

    IPC分类号： H01L21/00

    CPC分类号： H01L27/14625 ,  H01L27/14636 ,  H01L27/14685

    摘要： A semiconductor device has a semiconductor substrate including a light receiving element, a silicon oxide film formed on the semiconductor substrate, a plurality of wiring interlayer films formed on the silicon oxide film, and each including a wiring layer formed as the result of the fact that copper is buried, and a silicon nitride film formed on the wiring interlayer film of the uppermost layer wherein Si—H concentration is smaller than N—H concentration.

    摘要翻译： 半导体器件具有包括光接收元件的半导体衬底，形成在半导体衬底上的氧化硅膜，形成在氧化硅膜上的多个布线层间膜，并且每个包括布线层，其结果是， 铜被埋置，并且在最上层的布线层间膜上形成氮化硅膜，其中Si-H浓度小于N-H浓度。