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公开(公告)号：US20100269166A1
公开(公告)日：2010-10-21
申请号：US12621570
申请日：2009-11-19
IPC分类号： G06F21/20
摘要： In one embodiment, the invention is a method and apparatus for secure and reliable computing. One embodiment of an end-to-end security system for protecting a computing system includes a processor interface coupled to at least one of an application processor and an accelerator of the computing system, for receiving requests from the at least one of the application processor and the accelerator, a security processor integrating at least one embedded storage unit and connected to the processor interface with a tightly coupled memory unit for performing at least one of: authenticating, managing, monitoring, and processing the requests, and a data interface for communicating with a display, a network, and at least one embedded storage unit for securely holding at least one of data and programs used by the at least one of the application processor and the accelerator.
摘要翻译： 在一个实施例中，本发明是用于安全和可靠计算的方法和装置。 用于保护计算系统的端到端安全系统的一个实施例包括耦合到计算系统的应用处理器和加速器中的至少一个的处理器接口，用于接收来自应用处理器的至少一个和 加速器，集成至少一个嵌入式存储单元并且与处理器接口连接的紧密耦合的存储器单元的安全处理器，用于执行以下至少一个：认证，管理，监视和处理请求，以及数据接口，用于与 显示器，网络和至少一个嵌入式存储单元，用于安全地保持应用处理器和加速器中的至少一个使用的数据和程序中的至少一个。
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公开(公告)号：US08424071B2
公开(公告)日：2013-04-16
申请号：US12621570
申请日：2009-11-19
IPC分类号： G06F7/04
摘要： In one embodiment, the invention is a method and apparatus for secure and reliable computing. One embodiment of an end-to-end security system for protecting a computing system includes a processor interface coupled to at least one of an application processor and an accelerator of the computing system, for receiving requests from the at least one of the application processor and the accelerator, a security processor integrating at least one embedded storage unit and connected to the processor interface with a tightly coupled memory unit for performing at least one of: authenticating, managing, monitoring, and processing the requests, and a data interface for communicating with a display, a network, and at least one embedded storage unit for securely holding at least one of data and programs used by the at least one of the application processor and the accelerator.
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公开(公告)号：US20080186069A1
公开(公告)日：2008-08-07
申请号：US12099423
申请日：2008-04-08
申请人： Pascal A. Nsame , Anthony J. Perri , Lansing D. Pickup , Sebastian T. Ventrone , Matthew R. Welland
发明人： Pascal A. Nsame , Anthony J. Perri , Lansing D. Pickup , Sebastian T. Ventrone , Matthew R. Welland
IPC分类号： H03K3/00
CPC分类号： G11C5/145 , H03K3/356008
摘要： The invention comprises a design structure for a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.
摘要翻译： 本发明包括一种用于动态电压状态保存锁存电路的设计结构，其包括适于作为存储元件的充电装置，集成恢复机构，连接到充电装置的电源电压轨，分配给集成恢复机构的保持信号 ，分配给所述充电装置的数据信号输入，从充电装置分配的数据信号和分配给充电装置的时钟信号，其中所述集成恢复机构保持充电装置的状态而与充电装置无关。
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公开(公告)号：US20080062748A1
公开(公告)日：2008-03-13
申请号：US11530981
申请日：2006-09-12
申请人： Pascal A. Nsame , Anthony J. Perri , Lansing U. Pickup , Sebastian T. Ventrone , Matthew R. Walland
发明人： Pascal A. Nsame , Anthony J. Perri , Lansing U. Pickup , Sebastian T. Ventrone , Matthew R. Walland
IPC分类号： G11C11/00
摘要： The invention comprises a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.
摘要翻译： 本发明包括一种动态电压状态保存锁存电路，其包括适于作为存储元件的充电装置，集成恢复机构，连接到充电装置的电源电压轨，分配给集成恢复机构的保持信号，数据信号 分配给所述充电装置的输入，从所述充电装置分配的数据信号以及分配给所述充电装置的时钟信号，其中所述集成恢复机构保持所述充电装置的状态而与所述充电装置无关。
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公开(公告)号：US20090251474A1
公开(公告)日：2009-10-08
申请号：US12099183
申请日：2008-04-08
申请人： Deanna J. Chou , Jesse E. Craig , Pascal A. Nsame , John Sargis, JR. , Daneyand J. Singley , Sebastian T. Ventrone
发明人： Deanna J. Chou , Jesse E. Craig , Pascal A. Nsame , John Sargis, JR. , Daneyand J. Singley , Sebastian T. Ventrone
IPC分类号： G06T1/00
CPC分类号： G06T15/005 , G06T2200/16
摘要： A virtual computing and display system and method. The system includes a plurality of microprocessor-based devices which run software applications, and each microprocessor-based device generates at least one graphic processing unit command stream including a packet of graphic commands. The system further includes at least one communication network which directly receives the graphics processing unit command stream from each of the microprocessor-based devices and transfers each of the generated graphics processing unit command streams via a respective active channel, at least one multi-core adaptive display server which receives and processes the graphics processing unit command streams, and at least one display which receives the packets via the at least one active channel per user session and displays at least one image. The at least one active channel connects a respective microprocessor-based device, the communication network, the at least one multi-core adaptive display server and the at least one display.
摘要翻译： 虚拟计算和显示系统及方法。 该系统包括运行软件应用的多个基于微处理器的设备，并且每个基于微处理器的设备生成包括图形命令的分组的至少一个图形处理单元命令流。 该系统还包括至少一个通信网络，其直接从每个基于微处理器的设备接收图形处理单元命令流，并经由相应的活动信道传送每个生成的图形处理单元命令流，至少一个多核自适应 显示服务器，其接收和处理图形处理单元命令流，以及至少一个显示器，其通过每个用户会话的至少一个活动频道接收分组并显示至少一个图像。 所述至少一个活动通道连接相应的基于微处理器的设备，通信网络，至少一个多核自适应显示服务器和至少一个显示器。
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6.发明申请SYSTEM AND METHOD FOR DYNAMICALLY ADJUSTING PIPELINED DATA PATHS FOR IMPROVED POWER MANAGEMENT 审中-公开用于动态调整管道数据的系统和方法进行改进的电源管理公开(公告)号：US20070271449A1
公开(公告)日：2007-11-22
申请号：US11419388
申请日：2006-05-19
IPC分类号： G06F9/44
CPC分类号： G06F9/3869 , G06F9/3836 , G06F9/3859 , G06F9/3867 , G06F9/3873
摘要： A system for dynamically varying the pipeline depth of a computing device, depending upon at least one of computing function and workload, includes a state machine is configured to determine an optimum length of a pipeline architecture based on a processing function to be performed, and a pipeline sequence controller, responsive to the state machine, the pipeline sequence controller configured to vary the depth of the pipeline based on the determined optimum length. A plurality of clock splitter elements is associated with a corresponding plurality of latch stages in the pipeline architecture, the clock splitter elements coupled to the pipeline sequence controller and adapted to operate in a functional mode, one or more clock gating modes, and a pass-through flush mode. For each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith.
摘要翻译： 根据计算功能和工作负载中的至少一个动态地改变计算设备的流水线深度的系统包括状态机被配置为基于要执行的处理功能来确定流水线架构的最佳长度，以及 流水线序列控制器，响应于状态机，配置为基于所确定的最佳长度来改变管道的深度的流水线序列控制器。 多个时钟分离器元件与流水线架构中的对应的多个锁存级相关联，时钟分离器元件耦合到流水线序列控制器并且适于以功能模式操作，一个或多个时钟选通模式， 通过冲洗模式。 对于以直通冲洗模式工作的每个时钟分离器元件，数据通过相关联的锁存级而不与其相关联的时钟信号振荡。
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7.发明授权High bandwidth low-latency semaphore mapped protocol (SMP) for multi-core systems on chips 失效用于芯片上多核系统的高带宽低延迟信号量映射协议（SMP）公开(公告)号：US07765351B2
公开(公告)日：2010-07-27
申请号：US11684687
申请日：2007-03-12
IPC分类号： G06F12/00
CPC分类号： G06F9/526 , G06F9/544 , G06F15/167
摘要： A system and method for dynamically managing movement of semaphore data within the system. The system includes, but is no limited to, a plurality of functional units communicating over the network, a memory device communication with the plurality of functional units over the network, and at least one semaphore storage unit communicating with the plurality of functional unites and the memory device over the network. The plurality of functional units include a plurality of functional unit memory locations. The memory device includes a plurality of memory device memory locations. The at least one semaphore storage unit includes a plurality of semaphore storage unit memory locations. The at least one semaphore storage unit controls dynamic movement of the semaphore data among the plurality of functional unit memory locations, the plurality of memory device memory locations, the plurality of semaphore storage unit memory locations, and any combinations therof.
摘要翻译： 用于动态管理系统内信号量数据移动的系统和方法。 该系统包括但不限于通过网络通信的多个功能单元，与网络上的多个功能单元的存储设备通信，以及与多个功能单元通信的至少一个信号量存储单元，以及 存储设备通过网络。 多个功能单元包括多个功能单元存储单元。 存储器件包括多个存储器件存储器位置。 所述至少一个信号量存储单元包括多个信号量存储单元存储单元。 所述至少一个信号量存储单元控制所述多个功能单元存储器位置，所述多个存储器设备存储器位置，所述多个信号量存储单元存储器位置中的所述信号量数据的动态移动以及所述多个功能单元存储单元的任何组合。
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8.发明申请Design Structure for Localized Control Caching Resulting in Power Efficient Control Logic 审中-公开用于本地化控制缓存的设计结构，从而产生高效的控制逻辑公开(公告)号：US20080229074A1
公开(公告)日：2008-09-18
申请号：US12127860
申请日：2008-05-28
IPC分类号： G06F9/30
CPC分类号： G06F9/381 , G06F9/3867
摘要： A design structure for an integrated circuit (IC) including a decoder decoding instructions, shadow latches storing instructions as a localized loop, and a state machine controlling the decoder and the plurality of shadow latches. When the state machine identifies instructions that are the same as those stored in the localized loop, it deactivates the decoder and activates the plurality of shadow latches to retrieve and execute the localized loop in place of the instructions provided by the decoder. Additionally, a method of providing localized control caching operations in an IC to reduce power dissipation is provided. The method includes initializing a state machine to control the IC, providing a plurality of shadow latches, decoding a set of instructions, detecting a loop of decoded instructions, caching the loop of decoded instructions in the shadow latches as a localized loop, detecting a loop end signal for the loop and stopping the caching of the localized loop.
摘要翻译： 一种用于集成电路（IC）的设计结构，包括解码指令，存储指令作为局部回路的阴影锁存器，以及控制解码器和多个阴影锁存器的状态机。 当状态机识别与存储在本地化环路中的指令相同的指令时，其取消对解码器的激活，并激活多个阴影锁存器来取代并执行本地化的循环，代替解码器提供的指令。 另外，提供了一种在IC中提供局部控制高速缓存操作以减少功耗的方法。 该方法包括初始化状态机以控制IC，提供多个阴影锁存器，解码一组指令，检测解码指令的循环，将阴影锁存器中的解码指令的循环缓存为局部循环，检测循环 循环结束信号，并停止局部循环的缓存。
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公开(公告)号：US20070294519A1
公开(公告)日：2007-12-20
申请号：US11424943
申请日：2006-06-19
IPC分类号： G06F9/44
CPC分类号： G06F9/325 , G06F9/3808 , G06F9/381
摘要： An integrated circuit (IC) including a decoder decoding instructions, shadow latches storing instructions as a localized loop, and a state machine controlling the decoder and the plurality of shadow latches. When the state machine identifies instructions that are the same as those stored in the localized loop, it deactivates the decoder and activates the plurality of shadow latches to retrieve and execute the localized loop in place of the instructions provided by the decoder. Additionally, a method of providing localized control caching operations in an IC to reduce power dissipation is provided. The method includes initializing a state machine to control the IC, providing a plurality of shadow latches, decoding a set of instructions, detecting a loop of decoded instructions, caching the loop of decoded instructions in the shadow latches as a localized loop, detecting a loop end signal for the loop and stopping the caching of the localized loop.
摘要翻译： 包括解码指令，存储指令作为局部回路的阴影锁存器的集成电路（IC）以及控制解码器和多个阴影锁存器的状态机。 当状态机识别与存储在本地化环路中的指令相同的指令时，其取消对解码器的激活，并激活多个阴影锁存器来取代并执行本地化的循环，代替解码器提供的指令。 另外，提供了一种在IC中提供局部控制高速缓存操作以减少功耗的方法。 该方法包括初始化状态机以控制IC，提供多个阴影锁存器，解码一组指令，检测解码指令的循环，将阴影锁存器中的解码指令的循环缓存为局部循环，检测循环 循环结束信号，并停止局部循环的缓存。
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10.发明授权公开(公告)号：US08279861B2
公开(公告)日：2012-10-02
申请号：US12633149
申请日：2009-12-08
申请人： Chi-Chuen Chao-Suren , Ezran D. B. Hall , Pascal A. Nsame , Aydin Suren , Sebastian T. Ventrone
发明人： Chi-Chuen Chao-Suren , Ezran D. B. Hall , Pascal A. Nsame , Aydin Suren , Sebastian T. Ventrone
CPC分类号： G06F17/289 , H04L12/1827 , H04L65/1056 , H04L65/1069 , H04L65/605 , H04L65/607 , H04M3/42391 , H04M3/56 , H04M2203/2061
摘要： A computer-implemented method and system of enabling concurrent real-time multi-language communication between multiple participants using a selective broadcast protocol, the method including receiving at a first server a real-time communication from a first participant, the real-time communication being addressed to a second participant constructed in a first spoken language. A preferred spoken language of receipt of real-time communication is identified by the second participant. A determination is made whether the preferred spoken language of receipt is different than that of the first spoken language of the real-time communication. The real-time communication from the first spoken language is translated and delivered to the preferred spoken language of receipt of the second participant to create a translated real-time communication whenever the preferred spoken language is different than the first spoken language and forwarded without translation when the preferred spoken language of the second participant is the same as the preferred spoken language of the first participant.
摘要翻译： 一种使用选择性广播协议实现多个参与者之间的并发实时多语言通信的计算机实现的方法和系统，所述方法包括在第一服务器处接收来自第一参与者的实时通信，所述实时通信是 致力于以第一语言构建的第二参与者。 由第二参与者确定接收实时通信的首选语言。 确定接收的首选语言是否与实时通信的第一语言的语言不同。 当首选语言不同于第一语言时，来自第一语言的实时通信被翻译并且被传递到接收第二参与者的首选语言以便创建翻译的实时通信，并且在没有翻译的情况下转发 第二参与者的首选语言与第一参与者的首选语言相同。
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