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公开(公告)号：US08621132B2
公开(公告)日：2013-12-31
申请号：US11971080
申请日：2008-01-08
IPC分类号： G06F12/00
CPC分类号： G06F13/4243 , G11C5/04
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving first initialization data from a physical dual inline memory module (DIMM) and converting the first initialization data to second initialization data of a logical DIMM mapped to the physical DIMM. The example embodiment may further include programming a memory controller based on the second initialization data.
摘要翻译： 本文档还讨论了一个用于内存扩展的示例系统和方法。 示例实施例包括从物理双列直插式存储器模块（DIMM）接收第一初始化数据，并将第一初始化数据转换为映射到物理DIMM的逻辑DIMM的第二初始化数据。 该示例性实施例还可以包括基于第二初始化数据来编程存储器控制器。
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公开(公告)号：US20090177861A1
公开(公告)日：2009-07-09
申请号：US11971080
申请日：2008-01-08
IPC分类号： G06F9/34
CPC分类号： G06F13/4243 , G11C5/04
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving first initialization data from a physical dual inline memory module (DIMM) and converting the first initialization data to second initialization data of a logical DIMM mapped to the physical DIMM. The example embodiment may further include programming a memory controller based on the second initialization data.
摘要翻译： 本文档还讨论了一个用于内存扩展的示例系统和方法。 示例实施例包括从物理双列直插式存储器模块（DIMM）接收第一初始化数据，并将第一初始化数据转换为映射到物理DIMM的逻辑DIMM的第二初始化数据。 该示例性实施例还可以包括基于第二初始化数据来编程存储器控制器。
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公开(公告)号：US08825965B2
公开(公告)日：2014-09-02
申请号：US11971066
申请日：2008-01-08
CPC分类号： G06F12/1009 , G06F11/1016 , G06F12/0207 , G06F12/0292 , G06F12/0607 , G06F13/1684 , G06F13/4234
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel. Based on the memory request, the example embodiment includes selecting a location in memory to couple to a sub-channel of the channel and configuring the set of field effect transistors to couple the channel with the sub-channel. In the example embodiment, data may be allowed to flow between the memory controller and the location in the memory over the channel and the sub-channel.
摘要翻译： 本文档还讨论了一个用于内存扩展的示例系统和方法。 示例实施例包括通过信道从存储器控制器接收存储器请求。 基于存储器请求，示例性实施例包括选择存储器中的位置以耦合到信道的子信道并且配置该场效应晶体管集合以将该信道与子信道耦合。 在示例实施例中，可以允许数据通过信道和子信道在存储器控制器和存储器中的位置之间流动。
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公开(公告)号：US08407394B2
公开(公告)日：2013-03-26
申请号：US11971091
申请日：2008-01-08
IPC分类号： G06F12/00
CPC分类号： G06F12/0292 , G06F12/06
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes detecting a memory command directed to a logical rand and a number of physical ranks mapped to the logical rank. The example embodiment may also include issuing the memory command to the number of physical ranks based on determining that the memory command is to be issued to the number of physical ranks.
摘要翻译： 本文档还讨论了一个用于内存扩展的示例系统和方法。 示例实施例包括检测针对映射到逻辑秩的逻辑rand和多个物理等级的存储器命令。 该示例性实施例还可以包括基于确定存储器命令将被发布到物理等级的数量而将存储器命令发布到物理队列的数量。
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公开(公告)号：US20090177853A1
公开(公告)日：2009-07-09
申请号：US11971091
申请日：2008-01-08
IPC分类号： G06F12/00
CPC分类号： G06F12/0292 , G06F12/06
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes detecting a memory command directed to a logical rand and a number of physical ranks mapped to the logical rank. The example embodiment may also include issuing the memory command to the number of physical ranks based on determining that the memory command is to be issued to the number of physical ranks.
摘要翻译： 本文档还讨论了一个用于内存扩展的示例系统和方法。 示例实施例包括检测针对映射到逻辑秩的逻辑rand和多个物理等级的存储器命令。 该示例性实施例还可以包括基于确定存储器命令将被发布到物理等级的数量而将存储器命令发布到物理队列的数量。
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公开(公告)号：US20090177849A1
公开(公告)日：2009-07-09
申请号：US11971066
申请日：2008-01-08
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F11/1016 , G06F12/0207 , G06F12/0292 , G06F12/0607 , G06F13/1684 , G06F13/4234
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel. Based on the memory request, the example embodiment includes selecting a location in memory to couple to a sub-channel of the channel and configuring the set of field effect transistors to couple the channel with the sub-channel. In the example embodiment, data may be allowed to flow between the memory controller and the location in the memory over the channel and the sub-channel.
摘要翻译： 本文档还讨论了一个用于内存扩展的示例系统和方法。 示例实施例包括通过信道从存储器控制器接收存储器请求。 基于存储器请求，示例性实施例包括选择存储器中的位置以耦合到信道的子信道并且配置该场效应晶体管集合以将该信道与子信道耦合。 在示例实施例中，可以允许数据通过信道和子信道在存储器控制器和存储器中的位置之间流动。
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公开(公告)号：US5796732A
公开(公告)日：1998-08-18
申请号：US621720
申请日：1996-03-28
申请人： Mario Mazzola , Tom Edsall , Massimo Prati , Luca Cafiero
发明人： Mario Mazzola , Tom Edsall , Massimo Prati , Luca Cafiero
IPC分类号： H04L12/56 , H04L12/403
CPC分类号： H04L49/102 , H04L49/205 , H04L49/254 , H04L49/30 , H04L49/351
摘要： A switching bus architecture enables efficient transfer of data within a network switch having a plurality of ports interconnected by a high-performance switching bus. The architecture is preferably implemented as novel port interface and forwarding engine circuitry that cooperate to efficiently transmit data to, and receive data from, the switching bus in accordance with a 2-tier arbitration policy that ensures adequate port access to the bus. As a result of such a cooperating arrangement, the architecture improves the transfer efficiency of the switch by providing all ports sufficient bus access to convey accurate data throughout the switch.
摘要翻译： 交换总线架构能够在具有通过高性能交换总线互连的多个端口的网络交换机内进行有效的数据传输。 该架构优选地被实现为新颖的端口接口和转发引擎电路，其协作以根据确保对总线的足够端口访问的2级仲裁策略来有效地向交换总线传输数据和从交换总线接收数据。 作为这种协作安排的结果，该架构通过提供足够的总线访问来提供交换机的传输效率，从而在整个交换机中传送准确的数据。
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公开(公告)号：US5280500A
公开(公告)日：1994-01-18
申请号：US775641
申请日：1991-10-10
申请人： Mario Mazzola , Luca Cafiero , Maurilio DeNicolo
发明人： Mario Mazzola , Luca Cafiero , Maurilio DeNicolo
CPC分类号： H04L25/4917 , H03M5/18 , H03M5/20
摘要： A multilevel encoding scheme for transmitted data that encodes data in a multilevel code wherein the amplitude of any transition is always exactly one level during any time interval. A single-level transition between any two adjacent levels during a time interval represents a logical "1"; no transition during a time interval represents a logical "0". In a specific embodiment, modulation is limited to three defined amplitude levels equally space in amplitude and encoding is according to a three-level code. A four-bit to five-bit encoding scheme may be used to distribute bits for minimizing d.c. offset. The input data is preferably further scrambled to minimize aberrations in the emissions spectrum of signal carried over unshielded media.
摘要翻译： 用于对多级代码中的数据进行编码的传输数据的多级编码方案，其中在任何时间间隔期间任何转换的幅度总是正好为一级。 在一段时间间隔内任何两个相邻级别之间的单级转换代表逻辑“1”; 在时间间隔期间没有转换代表逻辑“0”。 在一个具体实施例中，调制被限制在三个定义的振幅水平上，幅度上相等的空间，并且根据三电平码进行编码。 可以使用四位到五位编码方案来分配比特以最小化直流。 抵消。 输入数据优选进一步加扰以最小化在非屏蔽介质上携带的信号的发射光谱中的像差。
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公开(公告)号：US5740171A
公开(公告)日：1998-04-14
申请号：US621718
申请日：1996-03-28
申请人： Mario Mazzola , Tom Edsall , Luca Cafiero
发明人： Mario Mazzola , Tom Edsall , Luca Cafiero
CPC分类号： H04L12/18 , H04L45/745 , H04L49/201 , H04L49/351 , H04L49/354
摘要： An address translation mechanism quickly and efficiently renders forwarding decisions for data flames transported among ports of a high-performance switch on the basis of, inter alia, virtual local area network (VLAN) associations among the ports. The translation mechanism comprises a plurality of forwarding tables, each of which contains entries having unique index values that translate to selection signals for ports destined to received the data frames. Each port is associated with a unique index value and a VLAN identifier to facilitate multicast data transfers within the switch at accelerated speeds and addressing capabilities.
摘要翻译： 地址转换机制在端口之间尤其是虚拟局域网（VLAN）关联的基础上，快速有效地呈现在高性能交换机的端口之间传输的数据火焰的转发决策。 翻译机制包括多个转发表，每个转发表包含具有唯一索引值的条目，其转换为用于接收数据帧的端口的选择信号。 每个端口与唯一的索引值和VLAN标识相关联，以促进交换机内加速速度和寻址能力的组播数据传输。
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10.发明授权Alternate Mark Invert (AMI) transceiver with switchable detection and digital precompensation 失效备用标记反相（AMI）收发器，具有可切换检测和数字预补偿
公开(公告)号：US4584690A
公开(公告)日：1986-04-22
申请号：US607998
申请日：1984-05-07
申请人： Luca Cafiero , Mario Mazzola , Massimo Prati
发明人： Luca Cafiero , Mario Mazzola , Massimo Prati
CPC分类号： H04L5/1492 , H04L25/4925
摘要： A high-speed digital transceiver is provided for use in a PBX environment comprising twisted-pair wire cables interconnecting like transceivers, each transceiver being operative to exchange voice, data and control information in a packetized format over a common twisted-pair cable. Specifically, each transceiver communicates packetized pulse code modulated information in pure Alternate Mark Inverted (AMI) coding, that is, without the introduction of bipolar violation pulses to provide timing. Frame synchronization is acquired on the first pulse by the use of a digital circuit deriving synchronization from a local high-speed clock. The use of a high-speed clock-driven digital circuit for synchronization acquisition eliminates the need for a phase-locked loop synchronization scheme and its concomitant finite acquisition delay. In addition, a receiving section employs a threshold selecting circuit which switches or makes thresholds in response to an expectation of the absence any bipolar violation in the transmitted signal. The effect of intersymbol interference are further minimized by provision of digital precompensation in the transmitted signal to maximize the slew rate between consecutive pulses. The precompensation scheme is based on a knowledge of the bit pattern and the amount of energy contained in a sequence of bits.
摘要翻译： 提供高速数字收发器用于PBX环境，包括互连在一起的收发器的双绞线电缆，每个收发器可操作以通过公共双绞线电缆以分组格式交换语音，数据和控制信息。 具体来说，每个收发器在纯交替标记反转（AMI）编码中传送分组化脉冲编码调制信息，即不引入双向违规脉冲来提供定时。 通过使用从本地高速时钟导出同步的数字电路，在第一脉冲上获取帧同步。 使用高速时钟驱动数字电路进行同步采集，无需采用锁相环同步方案及其伴随的有限采集延迟。 此外，接收部分采用阈值选择电路，该阈值选择电路响应于在所发送的信号中不存在任何双向违规的期望来切换或产生阈值。 通过在发送信号中提供数字预补偿来最大化连续脉冲之间的转换速率，进一步使码间干扰的影响最小化。 预补偿方案基于比特模式和包含在比特序列中的能量的量的知识。
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