公开(公告)号：US4245304A

公开(公告)日：1981-01-13

申请号：US968312

申请日：1978-12-11

申请人： Marion G. Porter ,  Robert W. Norman, Jr. ,  William A. Shelly

发明人： Marion G. Porter ,  Robert W. Norman, Jr. ,  William A. Shelly

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0859 ,  G06F12/0846 ,  G06F12/0855

摘要： A cache system includes a high speed storage unit organized into a plurality of levels, each including a number of multiword blocks and at least one multiposition address selection switch and address register. The address switch is connected to receive address signals from a plurality of address sources. The system further includes a directory organized into a plurality of levels for storing address information required for accessing blocks from the cache storage unit and timing circuits for defining first and second halves of a cache cycle of operation. Control circuits coupled to the timing circuits generate control signals for controlling the operation of the address selection switch. During the previous cycle, the control circuits condition the address selector switch to select an address which is loaded into the address register during the previous half cycle. This enables either the accessing of instructions from cache or the writing of data into cache during the first half of the next cache cycle. During the first half of the cycle, the address selected by the address switch in response to control signals from the control circuits is clocked into the address register. This permits processor operations, such as the accessing of operand data or the writing of data into cache to be performed during the second half of the same cycle.

摘要翻译： 缓存系统包括组织成多个级别的高速存储单元，每个级别包括多个多个块和至少一个多位地址选择开关和地址寄存器。 地址开关被连接以从多个地址源接收地址信号。 该系统还包括组织成多个级别的目录，用于存储从高速缓存存储单元访问块所需的地址信息和用于定义高速缓存操作周期的第一和第二半的定时电路。 耦合到定时电路的控制电路产生用于控制地址选择开关的操作的控制信号。 在上一个周期期间，控制电路使地址选择器开关状态选择在前半个周期内加载到地址寄存器中的地址。 这可以在下一个高速缓存周期的前一半期间访问来自高速缓存的指令或将数据写入高速缓存。 在周期的前一半期间，地址开关响应于来自控制电路的控制信号选择的地址被计时到地址寄存器中。 这允许诸如访问操作数数据或将数据写入高速缓存的处理器操作在相同周期的后半段期间执行。

公开(公告)号：US4208716A

公开(公告)日：1980-06-17

申请号：US968521

申请日：1978-12-11

申请人： Marion G. Porter ,  William A. Shelly ,  Robert W. Norman, Jr.

发明人： Marion G. Porter ,  William A. Shelly ,  Robert W. Norman, Jr.

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0855 ,  G06F12/0846 ,  G06F12/0859

摘要： A cache system includes a storage unit organized into a plurality of levels, each including a number of multiword blocks and a corresponding number of address selection switches and address registers. Each address selection switch has a plurality of different positions connected to receive address signals from a plurality of address sources. A decoder circuit generates output signals for controlling the operation of the address selection switches. In response to previously defined level signals, the decoder circuit conditions a specified one of the number of switches to switch from a first position to a second position. An address specifying the location into which memory data is to be written is clocked into one address register while the address specifying the location from which an instruction is to be fetched is clocked into the remaining address registers. A comparator circuit compares signals indicating the level into which memory data is to be written with signals indicating the level from which a next instruction is to be fetched. The comparator circuit generates signals which cause the delay of instruction access when there is a conflict between writing memory data and accessing instructions.

摘要翻译： 缓存系统包括组织成多个级别的存储单元，每个级别包括多个字块数量和相应数量的地址选择开关和地址寄存器。 每个地址选择开关具有连接以从多个地址源接收地址信号的多个不同位置。 解码器电路产生用于控制地址选择开关的操作的输出信号。 响应于先前定义的电平信号，解码器电路调节从第一位置切换到第二位置的开关数目中指定的一个。 指定要写入存储器数据的位置的地址被计时到一个地址寄存器中，而指定要从其获取指令的位置的地址被计时到其余的地址寄存器中。 比较器电路将指示要写入的存储器数据的电平的信号与指示下一条指令要从其获取的电平的信号进行比较。 当写入存储器数据和访问指令之间存在冲突时，比较器电路产生导致指令访问延迟的信号。

公开(公告)号：US4217640A

公开(公告)日：1980-08-12

申请号：US968522

申请日：1978-12-11

申请人： Marion G. Porter ,  Charles P. Ryan ,  William A. Shelly

发明人： Marion G. Porter ,  Charles P. Ryan ,  William A. Shelly

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0855

摘要： A data processing system comprises a data processing unit coupled to a cache unit which couples to a main store. The cache unit includes a cache store organized into a plurality of levels, each for storing a number of blocks of information in the form of data and instructions. Directories associated with the cache store contain addresses and level control information for indicating which blocks of information reside in the cache store. The cache unit further includes control apparatus and a transit block buffer comprising a number of sections each having a plurality of locations for storing read commands and transit block addresses associated therewith. A corresponding number of valid bit storage elements are included, each of which is set to a binary ONE state when a read command and the associated transit block address are loaded into a corresponding one of the buffer locations. Comparison circuits, coupled to the transit block buffer, compare the transit block address of each outstanding read command stored in the transit block buffer section with the address of each read command or write command received from the processing unit. When there is a conflict, the comparison circuits generate an output signal which conditions the control apparatus to hold or stop further processing of the command by the cache unit and the operation of the processing unit. Holding lasts until the valid bit storage element of the location storing the outstanding read command is reset to a binary ZERO indicating that execution of the read command is completed.

摘要翻译： 数据处理系统包括耦合到耦合到主存储器的高速缓存单元的数据处理单元。 高速缓存单元包括组织成多个级别的缓存存储器，每个级别用于以数据和指令的形式存储多个信息块。 与高速缓存存储相关联的目录包含用于指示哪些信息块驻留在高速缓存存储器中的地址和级别控制信息。 高速缓存单元还包括控制装置和传输块缓冲器，其包括多个部分，每个部分具有用于存储读取命令的多个位置和与其相关联的传输块地址。 包括相应数量的有效位存储元件，当将读取命令和相关联的传输块地址加载到相应的一个缓冲器位置时，其中的每一个被设置为二进制ONE状态。 耦合到传输块缓冲器的比较电路将存储在传输块缓冲器部分中的每个未完成读取命令的传输块地址与从处理单元接收的每个读取命令或写入命令的地址进行比较。 当存在冲突时，比较电路产生输出信号，该输出信号使控制装置保持或停止高速缓存单元对命令的进一步处理和处理单元的操作。 持续持续，直到存储未完成读取命令的位置的有效位存储元件被重置为指示执行读命令的二进制零。

公开(公告)号：US3976977A

公开(公告)日：1976-08-24

申请号：US562317

申请日：1975-03-26

申请人： Marion G. Porter ,  Garvin Wesley Patterson ,  William A. Shelly ,  Nicolas S. Lemak

发明人： Marion G. Porter ,  Garvin Wesley Patterson ,  William A. Shelly ,  Nicolas S. Lemak

IPC分类号： G06F13/12 ,  G06F3/00 ,  G06F15/20

CPC分类号： G06F13/124

摘要： An input-output processing system (IOPS) which performs both the communication and control functions in a large scale data processing system is disclosed. By relieving the main data processor of these functions more efficient use of the entire system is made possible. The IOPS includes a processor to develop addresses for a paged memory and institute execution of input-output command sequences.

摘要翻译： 公开了一种在大规模数据处理系统中执行通信和控制功能的输入输出处理系统（IOPS）。 通过减轻这些功能的主数据处理器，可以更有效地使用整个系统。 IOPS包括处理器，用于开发分页存储器的地址并执行输入 - 输出命令序列。

公开(公告)号：US06480973B1

公开(公告)日：2002-11-12

申请号：US09409456

申请日：1999-09-30

申请人： William A. Shelly ,  David A. Egolf ,  Wayne R. Buzby

发明人： William A. Shelly ,  David A. Egolf ,  Wayne R. Buzby

IPC分类号： G06F1100

CPC分类号： G06F9/526

摘要： In a NUMA architecture, processors in the same CPU module with a processor opening a spin gate tend to have preferential access to a spin gate in memory when attempting to close the spin gate. This “unfair” memory access to the desired spin gate can result in starvation of processors from other CPU modules. This problem is solved by “balking” or delaying a specified period of time before attempting to close a spin gate whenever either one of the processors in the same CPU module just opened the desired spin gate, or when a processor in another CPU module is spinning trying to close the spin gate. Each processor detects when it is spinning on a spin gate. It then transmits that information to the processors in other CPU modules, allowing them to balk when opening spin gates.

摘要翻译： 在NUMA体系结构中，与打开自旋门的处理器相同的CPU模块中的处理器在尝试关闭旋转门时倾向于优先访问存储器中的自旋门。 对所需旋转门的这种“不公平”存储器访问可能导致处理器从其他CPU模块的饥饿。 在同一个CPU模块中的任何一个处理器刚刚打开所需的旋转门之前，或者当另一个CPU模块中的处理器旋转时，这个问题就是在尝试关闭旋转门之前“指定一段时间”来解决 试图关闭旋转门。 每个处理器检测何时在旋转门上旋转。 然后将该信息发送到其他CPU模块中的处理器，允许它们在打开旋转门时阻塞。

公开(公告)号：US4000487A

公开(公告)日：1976-12-28

申请号：US562362

申请日：1975-03-26

申请人： Garvin Wesley Patterson ,  William A. Shelly ,  Earnest M. Monahan

发明人： Garvin Wesley Patterson ,  William A. Shelly ,  Earnest M. Monahan

IPC分类号： G06F9/46 ,  G06F13/00 ,  G06F13/14 ,  G06F13/22 ,  G06F13/26 ,  G06F13/40 ,  G06F3/00

CPC分类号： G06F13/22 ,  G06F13/26 ,  G06F13/4022

摘要： An input/output processing system includes a plurality of active modules, a plurality of passive modules, at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. The active modules include an input/output processing unit which processes interrupts and executes command sequences and a multiplexer unit which directly controls transfers between the memory module and any one of the peripheral devices coupled to different ones of a plurality of ports of the multiplexer unit. The system interface unit which operatively provides connections between the different modules includes apparatus for generating steering codes defining the physical location of each module requiring service by another module of the system. The system interface unit appends information provided by the particular module generating a requesting request for attention to the steering code generated. The generation of steering code information by the system interface unit and the module included in such requests insures that only authorized accesses are made to the different modules during the input/output processing unit's execution of programs during the running of processes associated therewith.

摘要翻译： 输入/输出处理系统包括多个有源模块，多个无源模块，至少一个存储器模块和具有多个端口的系统接口单元，每个端口连接到不同的模块之一。 有源模块包括处理中断并执行命令序列的输入/输出处理单元和直接控制存储器模块与耦合到多路复用器单元的多个端口中的不同端口的任何外围设备之间的传输的多路复用器单元。 可操作地提供不同模块之间的连接的系统接口单元包括用于产生定义需要系统的另一个模块进行服务的每个模块的物理位置的转向代码的装置。 系统接口单元附加由特定模块提供的信息，产生请求请求，以产生注意力。 由系统接口单元和包括在该请求中的模块产生导向码信息确保在输入/输出处理单元在与其相关的进程运行期间执行程序期间仅对不同模块进行授权访问。

公开(公告)号：US06484272B1

公开(公告)日：2002-11-19

申请号：US09409811

申请日：1999-09-30

申请人： David A. Egolf ,  William A. Shelly ,  Wayne R. Buzby

发明人： David A. Egolf ,  William A. Shelly ,  Wayne R. Buzby

IPC分类号： G06F100

CPC分类号： G06F9/526

摘要： In a NUMA architecture, processors in the same CPU module with a processor opening a spin gate tend to have preferential access to a spin gate in memory when attempting to close the spin gate. This “unfair” memory access to the desired spin gate can result in starvation of processors from other CPU modules. This problem is solved by “balking” or delaying a specified period of time before attempting to close a spin gate whenever either one of the processors in the same CPU module just opened the desired spin gate, or when a processor in another CPU module is spinning trying to close the spin gate. Each processor detects when it is spinning on a spin gate. It then transmits that information to the processors in other CPU modules, allowing them to balk when opening spin gates.

摘要翻译： 在NUMA体系结构中，与打开自旋门的处理器相同的CPU模块中的处理器在尝试关闭旋转门时倾向于优先访问存储器中的自旋门。 对所需旋转门的这种“不公平”存储器访问可能导致处理器从其他CPU模块的饥饿。 在同一个CPU模块中的任何一个处理器刚刚打开所需的旋转门之前，或者当另一个CPU模块中的处理器旋转时，这个问题就是在尝试关闭旋转门之前“指定一段时间”来解决 试图关闭旋转门。 每个处理器检测何时在旋转门上旋转。 然后将该信息发送到其他CPU模块中的处理器，允许它们在打开旋转门时阻塞。

公开(公告)号：US06223228B1

公开(公告)日：2001-04-24

申请号：US09156377

申请日：1998-09-17

申请人： Charles P. Ryan ,  William A. Shelly ,  Ronald W. Yoder

发明人： Charles P. Ryan ,  William A. Shelly ,  Ronald W. Yoder

IPC分类号： G06F112

CPC分类号： G06F9/30087 ,  G06F1/04 ,  G06F11/2236 ,  G06F11/3466

摘要： Two instructions are provided to synchronize multiple processors (92) in a data processing system (80). A Transmit Sync instruction (TSYNC) transmits a synchronize processor interrupt (276) to all of the active processors (92) in the system (80). Processors (92) wait for receipt of the synchronize signal (278) by executing a Wait for Sync (WSYNC) instruction. Each of the processors waiting for such a signal (278) is activated at the next clock cycle after receipt of the interrupt signal (278). An optional timeout value is provided to protect against hanging a waiting processor (92) that misses the interrupt (278). Whenever the WSYNC instruction is activated by receipt of the interrupt (278), a trace is started to trace a fixed number of events to an internal Trace Cache (58).

摘要翻译： 提供两个指令以同步数据处理系统（80）中的多个处理器（92）。 发送同步指令（TSYNC）向系统（80）中的所有活动处理器（92）发送同步处理器中断（276）。 处理器（92）通过执行等待同步（WSYNC）指令等待接收同步信号（278）。 等待这种信号（278）的每个处理器在接收到中断信号（278）之后的下一个时钟周期被激活。 提供可选的超时值以防止挂起错过中断的等待处理器（92）（278）。 每当通过接收到中断（278）激活WSYNC指令时，将启动跟踪以将固定数量的事件跟踪到内部跟踪缓存（58）。

公开(公告)号：US4858176A

公开(公告)日：1989-08-15

申请号：US145845

申请日：1988-01-19

申请人： John E. Wilhite ,  William A. Shelly

发明人： John E. Wilhite ,  William A. Shelly

IPC分类号： G06F9/38

CPC分类号： G06F9/3867

摘要： A distrbutor for the central execution pipeline unit of a central processor of a data processing system, which central processor has a plurality of execution units. The distributor serves as a communications center by which machine words, such as operands, are transmitted primarily from the cache unit of the central processor unit to execution units and the instruction fetch unit of the central processor unit. Some machine words are transmitted directly from the collector unit to selected units and others are transmitted after being stored in the data register of the distributor. Machine words stored in the data register can be realigned if required by an instruction by character or word alignment switches. The aligned words are then stored in the data register means prior to their being transmitted to units of the central processor. Other sources of signals transmitted by the distributor are the collector unit and registers of the distributor containing the effective address of a target word as calculated by the central execution pipeline unit, as well as copies of machine words in key registers, the A/Q registers, of certain of the execution units.

摘要翻译： 用于数据处理系统的中央处理器的中央执行流水线单元的分配器，该中央处理器具有多个执行单元。 分配器用作通信中心，机器字（诸如操作数）主要从中央处理器单元的高速缓存单元传送到中央处理器单元的执行单元和指令提取单元。 一些机器字从收集器单元直接发送到所选单元，而其他机器字被存储在分配器的数据寄存器中之后被发送。 存储在数据寄存器中的机器字可以通过字符或字对齐开关的指令进行调整。 然后将对齐的字在其被发送到中央处理器的单元之前存储在数据寄存器装置中。 由分配器发送的其他信号源是收集器单元和分配器的寄存器，其包含由中央执行流水线单元计算的目标字的有效地址，以及密钥寄存器中的机器字的副本，A / Q寄存器 ，某些执行单位。

公开(公告)号：US06754859B2

公开(公告)日：2004-06-22

申请号：US09752924

申请日：2001-01-03

申请人： Bruce E. Hayden ,  William A. Shelly

发明人： Bruce E. Hayden ,  William A. Shelly

IPC分类号： G11C2900

CPC分类号： G06F13/1663 ,  G06F12/0815

摘要： A plurality of processors in a data processing system share a common memory through which they communicate and share resources. When sharing resources, one processor needs to wait for another processor to modify a specified location in memory, such as unlocking a lock. Memory and bus traffic are minimized during this waiting by first reading and testing the memory location. Then, the memory location is not read and tested again until the local copy of the cache line containing that memory location is invalidated by another processor. This feature is utilized both for a Lock instruction and a Wait for Change instruction, both of which utilize a timer parameter for specifying a maximum number of cycles to wait for another processor to modify the specified location in memory.

摘要翻译： 数据处理系统中的多个处理器共享共同的存储器，通过它们进行通信和共享资源。 当共享资源时，一个处理器需要等待另一个处理器来修改存储器中的指定位置，例如解锁锁定。 在这个等待期间，通过读取和测试存储器位置，使存储器和总线流量最小化。 然后，直到含有该存储器位置的高速缓存行的本地副本被其他处理器无效之后，才会再次读取和测试存储器位置。 该功能既用于锁定指令和等待更改指令，两者都利用定时器参数来指定最大循环次数，以等待另一个处理器修改存储器中的指定位置。