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公开(公告)号：US20060253523A1
公开(公告)日：2006-11-09
申请号：US11123702
申请日：2005-05-09
申请人： Mark Anders , Sanu Mathew , Nanda Siddaiah , Sapumal Wijeratne
发明人： Mark Anders , Sanu Mathew , Nanda Siddaiah , Sapumal Wijeratne
IPC分类号： G06F7/50
摘要： An adder circuit is provided that includes a propagate and generate circuit stage to provide propagate and generate signals, a plurality of carry-merge stages to provide carry signals based on the propagate and generate signals and a conditional sum generator to provide conditional sums based on the propagate and generate signals. The conditional sum generator includes ripple carry gates and XOR logic gates. The adder circuit also includes a plurality of multiplexers to receive the carry signals and the conditional sums and to provide an output based on the input signals.
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公开(公告)号：US20050125481A1
公开(公告)日：2005-06-09
申请号：US10728127
申请日：2003-12-04
申请人： Sanu Mathew , Mark Anders , Ram Krishnamurthy , Sapumal Wijeratne
发明人： Sanu Mathew , Mark Anders , Ram Krishnamurthy , Sapumal Wijeratne
摘要： An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate the multiple input data bits. The combination of the multiplexing network and the sense amplifier acts as the state-holding element at the input of the adder, avoiding the overheads of an explicit latch stage.
摘要翻译： 一个加法器电路包括多个选择器和一个加法器。 选择器为加法器提供多个输入数据位。 每个选择器包括复用网络和读出放大器的组合，以从多个输入值中选择以产生多个输入数据位。 复用网络和读出放大器的组合在加法器的输入端作为状态保持元件，避免显式锁存级的开销。
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公开(公告)号：US07509368B2
公开(公告)日：2009-03-24
申请号：US11123702
申请日：2005-05-09
IPC分类号： G06F7/50
摘要： An adder circuit is provided that includes a propagate and generate circuit stage to provide propagate and generate signals, a plurality of carry-merge stages to provide carry signals based on the propagate and generate signals and a conditional sum generator to provide conditional sums based on the propagate and generate signals. The conditional sum generator includes ripple carry gates and XOR logic gates. The adder circuit also includes a plurality of multiplexers to receive the carry signals and the conditional sums and to provide an output based on the input signals.
摘要翻译： 提供了一种加法器电路，其包括传播和产生电路级以提供传播和产生信号;多个进位合并级，用于基于传播和产生信号提供进位信号;以及条件和发生器，以基于 传播和产生信号。 条件和生成器包括纹波进位门和异或逻辑门。 加法器电路还包括多个多路复用器，用于接收进位信号和条件和，并且基于输入信号提供输出。
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公开(公告)号：US20050068065A1
公开(公告)日：2005-03-31
申请号：US10676345
申请日：2003-09-30
申请人： Sapumal Wijeratne
发明人： Sapumal Wijeratne
IPC分类号： H03K3/012 , H03K3/037 , H03K3/3562 , H03K19/094
CPC分类号： H03K3/35625 , H03K3/012 , H03K3/0372
摘要： An apparatus comprising a low voltage swing (LVS) circuit having a plurality of alternating LVS pre-charging and evaluation phases and a select logic circuit coupled to the LVS circuit and responsive to a plurality of input data signals to generate a plurality of select signals for the LVS circuit. Each of the select signals occurs during one of the LVS evaluation phases and has a turning-on edge and a turning-off edge. The turning-off edge of each of the select signals is generated independent of the input data signals.
摘要翻译： 一种装置，包括具有多个交替的LVS预充电和评估阶段的低电压摆动（LVS）电路和耦合到LVS电路的选择逻辑电路，并且响应于多个输入数据信号以产生多个选择信号 LVS电路。 每个选择信号发生在LVS评估阶段期间，并且具有接通边缘和关闭边缘。 每个选择信号的关断边缘独立于输入数据信号产生。
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公开(公告)号：US07325024B2
公开(公告)日：2008-01-29
申请号：US10728127
申请日：2003-12-04
IPC分类号： G06F7/50
摘要： An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate the multiple input data bits. The combination of the multiplexing network and the sense amplifier acts as the state-holding element at the input of the adder, avoiding the overheads of an explicit latch stage.
摘要翻译： 一个加法器电路包括多个选择器和一个加法器。 选择器为加法器提供多个输入数据位。 每个选择器包括复用网络和读出放大器的组合，以从多个输入值中选择以产生多个输入数据位。 复用网络和读出放大器的组合在加法器的输入端作为状态保持元件，避免显式锁存级的开销。
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公开(公告)号：US06922082B2
公开(公告)日：2005-07-26
申请号：US10676345
申请日：2003-09-30
申请人： Sapumal Wijeratne
发明人： Sapumal Wijeratne
IPC分类号： H03K3/012 , H03K3/037 , H03K3/3562 , H03K19/094
CPC分类号： H03K3/35625 , H03K3/012 , H03K3/0372
摘要： An apparatus comprising a low voltage swing (LVS) circuit having a plurality of alternating LVS pre-charging and evaluation phases and a select logic circuit coupled to the LVS circuit and responsive to a plurality of input data signals to generate a plurality of select signals for the LVS circuit. Each of the select signals occurs during one of the LVS evaluation phases and has a turning-on edge and a turning-off edge. The turning-off edge of each of the select signals is generated independent of the input data signals.
摘要翻译： 一种装置，包括具有多个交替的LVS预充电和评估阶段的低电压摆动（LVS）电路和耦合到LVS电路的选择逻辑电路，并且响应于多个输入数据信号以产生多个选择信号 LVS电路。 每个选择信号发生在LVS评估阶段期间，并且具有接通边缘和关闭边缘。 每个选择信号的关断边缘独立于输入数据信号产生。
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公开(公告)号：US20060031280A1
公开(公告)日：2006-02-09
申请号：US10911824
申请日：2004-08-04
申请人： Sapumal Wijeratne
发明人： Sapumal Wijeratne
IPC分类号： G06F7/50
CPC分类号： G06F7/506
摘要： A multi-bit adder includes a carry chain, a carry-skip network, sum cells, and a carry-sum cell. The carry chain propagates, generates, or kills carry-in bits. The carry-skip network is coupled to the carry chain to selectively skip the carry-in bits over at least one portion of the carry chain. The sum cells are coupled along the carry chain to sum the carry-in bits with corresponding bits of two operands to generate a multi-bit resultant. The carry-sum cell is coupled to receive one of the carry-in bits to a single intermediate bit position on the carry chain and to generate one bit of the multi-bit resultant having a more significant bit position than the single intermediate bit position.
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公开(公告)号：US20050169074A1
公开(公告)日：2005-08-04
申请号：US10769172
申请日：2004-01-30
申请人： Sapumal Wijeratne
发明人： Sapumal Wijeratne
IPC分类号： G11C7/00 , H03K19/096
CPC分类号： H03K19/0963
摘要： A circuit comprises an evaluate clock trace to receive an evaluate clock signal and a precharge clock trace to receive a precharge clock signal. The circuit further comprises sample circuitry coupled to a first signal trace, a second signal trace, the precharge clock trace and the evaluate clock trace to facilitate a detection of a transition on the first signal trace from a first voltage level to a second voltage level. In addition, the circuit comprises latch circuitry coupled to the first signal trace, the second signal trace, the precharge clock trace and the evaluate clock trace to utilize at least a portion of the sample circuitry to maintain voltage levels on the first and the second signal traces when an evaluate clock and a precharge clock are inactive.
摘要翻译： 电路包括评估时钟跟踪以接收评估时钟信号和预充电时钟跟踪以接收预充电时钟信号。 电路还包括耦合到第一信号迹线，第二信号迹线，预充电时钟迹线和评估时钟迹线的采样电路，以便于检测第一信号迹线上的从第一电压电平到第二电压电平的转变。 此外，电路包括耦合到第一信号迹线，第二信号迹线，预充电时钟迹线和评估时钟迹线的锁存电路，以利用采样电路的至少一部分来维持第一和第二信号上的电压电平 评估时钟和预充电时钟不活动时的踪迹。
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公开(公告)号：US20050168244A1
公开(公告)日：2005-08-04
申请号：US10769257
申请日：2004-01-30
申请人： Sapumal Wijeratne
发明人： Sapumal Wijeratne
IPC分类号： H03K19/00 , H03K19/0185
CPC分类号： H03K19/01855
摘要： A circuit comprises a signal trace to receive a first large signal, a first plurality of signal traces to receive a small signal pair and a clock trace to receive a clock signal. The circuit further comprises a mixed signal circuit having at least a first and a second element, coupled to the signal trace, the first plurality of signal traces and the clock trace. The mixed signal circuit it to facilitate generation of a second large signal based at least in part on the small signal pair and the first large signal, with the first large signal and the clock signal driving the first and second elements respectively to transition asynchronously.
摘要翻译： 电路包括用于接收第一大信号的信号迹线，用于接收小信号对的第一多个信号迹线和用于接收时钟信号的时钟迹线。 电路还包括具有至少第一和第二元件的混合信号电路，耦合到信号迹线，第一多个信号迹线和时钟迹线。 所述混合信号电路至少部分地基于小信号对和第一大信号而产生第二大信号，其中第一大信号和时钟信号分别驱动第一和第二元件以异步地转换。
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10.发明授权Ultra low voltage, low leakage, high density, variation tolerant memory bit cells 有权超低电压，低泄漏，高密度，耐变容容量的存储单元公开(公告)号：US07656702B2
公开(公告)日：2010-02-02
申请号：US12006288
申请日：2007-12-31
IPC分类号： G11C11/40
CPC分类号： G11C11/412
摘要： Methods and apparatus to provide ultra low voltage, low leakage, high density, and/or variation tolerant memory bit cells are described. In one embodiment, each of the cross-coupled invertors of a memory cell may include a plurality of p-channel transistors. Other embodiments are also described.
摘要翻译： 描述了提供超低电压，低泄漏，高密度和/或变化容限的存储器位单元的方法和装置。 在一个实施例中，存储器单元的交叉耦合反相器中的每一个可以包括多个p沟道晶体管。 还描述了其它实施例。
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