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1.发明申请Using Extreme Data Rate Memory Commands to Scrub and Refresh Double Data Rate Memory 审中-公开使用极限数据速率存储器命令来刷新和刷新双倍数据速率存储器公开(公告)号：US20080183916A1
公开(公告)日：2008-07-31
申请号：US11668531
申请日：2007-01-30
申请人： Mark David Bellows , Paul Allen Ganfield , Ryan Abel Heckendorf , John David Irish , David Alan Norgaard , Ibrahim Abdel-Rahman Ouda , Tolga Ozguner
发明人： Mark David Bellows , Paul Allen Ganfield , Ryan Abel Heckendorf , John David Irish , David Alan Norgaard , Ibrahim Abdel-Rahman Ouda , Tolga Ozguner
IPC分类号： G06F13/00
CPC分类号： G06F11/106
摘要： In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a processor adapted to issue a command complying with a first protocol; (2) providing a memory coupled to the processor and accessible by a command complying with a second protocol; (3) employing a plurality of scrub commands complying with the second protocol to check respective portions of the memory for errors, wherein each scrub command complying with the second protocol is a converted version of a scrub command complying with the first protocol issued by the processor and the respective portions are non-sequential; and (4) refreshing bits stored in the entire memory within a predetermined time period. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）提供适于发出符合第一协议的命令的处理器; （2）提供耦合到所述处理器的存储器，并且可通过符合第二协议的命令来访问; （3）采用符合第二协议的多个擦除命令来检查存储器的相应部分的错误，其中符合第二协议的每个擦除命令是符合由处理器发出的第一协议的擦除命令的转换版本 并且各部分是非顺序的; 和（4）在预定时间段内刷新存储在整个存储器中的位。 提供了许多其他方面。
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2.发明申请公开(公告)号：US20080168298A1
公开(公告)日：2008-07-10
申请号：US11620104
申请日：2007-01-05
申请人： Mark David Bellows , Paul Allen Ganfield , David Alan Norgaard , Ibrahim Abdel-Rahman Ouda , Tolga Ozguner
发明人： Mark David Bellows , Paul Allen Ganfield , David Alan Norgaard , Ibrahim Abdel-Rahman Ouda , Tolga Ozguner
CPC分类号： G11C7/10 , G11C2207/2254
摘要： In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a computer system including (a) a memory; (b) a processor adapted to issue a functional command to the memory; (c) a translation chip; (d) a first link adapted to couple the processor to the translation chip; and (e) a second link adapted to couple the translation chip to the memory; (2) calibrating the first link using the translation chip; and (3) while calibrating the first link, calibrating the second link using the translation chip. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）提供一种包括（a）存储器的计算机系统; （b）适于向存储器发出功能命令的处理器; （c）翻译芯片; （d）适于将所述处理器耦合到所述翻译芯片的第一链接; 和（e）适于将所述翻译芯片耦合到所述存储器的第二链接; （2）使用翻译芯片校准第一链接; 和（3）在校准第一链路的同时，使用转换芯片校准第二链路。 提供了许多其他方面。
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公开(公告)号：US20080168206A1
公开(公告)日：2008-07-10
申请号：US11620110
申请日：2007-01-05
申请人： Mark David Bellows , Paul Allen Ganfield , Kent Harold Haselhorst , Ryan Abel Heckendorf , Ibrahim Abdel-Rahman Ouda , Tolga Ozguner
发明人： Mark David Bellows , Paul Allen Ganfield , Kent Harold Haselhorst , Ryan Abel Heckendorf , Ibrahim Abdel-Rahman Ouda , Tolga Ozguner
IPC分类号： G06F13/14
CPC分类号： G06F13/4059
摘要： In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a computer system including (a) a first memory; (b) a processor adapted to issue a functional command to the first memory; (c) a translation chip; (d) a cache memory coupled to the translation chip; (e) a first link adapted to couple the processor to the translation chip; and (f) a second link adapted to couple the translation chip to the first memory; and (2) calibrating the first link to transmit data between the processor and cache memory. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）提供一种包括（a）第一存储器的计算机系统; （b）适于向第一存储器发出功能命令的处理器; （c）翻译芯片; （d）耦合到所述平移芯片的高速缓冲存储器; （e）适于将所述处理器耦合到所述翻译芯片的第一链接; 和（f）适于将所述翻译芯片耦合到所述第一存储器的第二链路; 和（2）校准第一链路以在处理器和高速缓冲存储器之间传送数据。 提供了许多其他方面。
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4.发明申请APPARATUS FOR IMPLEMENTING ACTIONS BASED ON PACKET CLASSIFICATION AND LOOKUP RESULTS 审中-公开基于分组分类和查询结果执行操作的设备公开(公告)号：US20080198853A1
公开(公告)日：2008-08-21
申请号：US12106365
申请日：2008-04-21
IPC分类号： H04L12/28
CPC分类号： H04L47/10 , H04L47/2408 , H04L47/2441
摘要： A method and apparatus are provided for implementing predefined actions based upon packet classification and lookup results in a communications network processor. A plurality of sets of rules is defined. Each rule set includes at least one rule and each rule has a set of masked compares for comparing results of hits and misses of table lookups. Each masked compare set has an associated field for selecting an action. The action defines a set of one or more commands and each command defines a processing operation. One rule set is identified based upon the packet classification result for a received packet. When one of the rules is identified having a match of the masked compares, then the action of associated with the identified rule is selected. Otherwise a default action is provided responsive to no rule of the identified rule set having a match of the masked compares.
摘要翻译： 提供了一种基于通信网络处理器中的分组分类和查找结果来实现预定动作的方法和装置。 定义了多组规则。 每个规则集包括至少一个规则，每个规则具有一组掩码的比较，用于比较表查找的命中和未命中的结果。 每个被屏蔽的比较集合都有一个关联的字段用于选择一个动作。 该动作定义一组一个或多个命令，每个命令定义一个处理操作。 基于接收到的分组的分组分类结果来识别一个规则集。 当识别出其中一个规则具有被掩蔽的比较的匹配时，则选择与所识别的规则相关联的动作。 否则，响应于不具有所掩蔽的比较的匹配的所识别的规则集的规则来提供默认动作。
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公开(公告)号：US20120069729A1
公开(公告)日：2012-03-22
申请号：US12884389
申请日：2010-09-17
IPC分类号： H04L12/26
CPC分类号： H04L12/2602 , G06F11/0745 , G06F11/0793 , G06F13/4009 , H04L43/00 , H04W24/00 , H04W24/08 , H04W28/04
摘要： A method and circuit for implementing lane shuffle for fault-tolerant communication links, and a design structure on which the subject circuit resides are provided. Shuffle hardware logic steers a set of virtual data lanes onto a set of physical optical lanes, steering around all lanes that are detected as bad during link initialization training. A mask status register is loaded with a mask of lane fail information during link training, which flags the bad lanes, if any. The shuffle hardware logic uses a shift template, where each position in the starting template is a value representing the corresponding lane position. The shift template is cascaded through a set of shifters controlled by the fail mask.
摘要翻译： 一种用于实现用于容错通信链路的车道混洗的方法和电路，以及设置有该主题电路所在的设计结构。 随机的硬件逻辑将一组虚拟数据通道引导到一组物理光学通道上，在链路初始化训练期间绕着被检测为坏的所有通道转向。 在链路训练期间，掩码状态寄存器加载了通道故障信息的掩码，标志着不良通道（如果有的话）。 洗牌硬件逻辑使用移位模板，其中起始模板中的每个位置都是表示对应车道位置的值。 移位模板通过由失败掩码控制的一组移位器进行级联。
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公开(公告)号：US07809008B2
公开(公告)日：2010-10-05
申请号：US12049266
申请日：2008-03-14
IPC分类号： H04L12/28
CPC分类号： H04L45/54 , H04L45/02 , H04L45/742
摘要： In a first aspect, a first method is provided that includes the steps of (1) providing a pointer that includes a first keytype field and a second keytype field; and (2) assigning a value to the second keytype field of the pointer based on a tabletype field of an updated table. The updated table is an updated version of a first table written in a memory, and the first keytype field of the pointer has a value assigned based on a tabletype field of the first table. The first method further includes the step of employing the second keytype field of the pointer to point to the updated table. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了一种包括以下步骤的第一方法：（1）提供包括第一键类型字段和第二键类型字段的指针; 和（2）基于更新表的表格类型字段将值分配给指针的第二键类型字段。 更新的表是写入存储器的第一表的更新版本，并且指针的第一键类型字段具有基于第一表的表类型字段分配的值。 第一方法还包括采用指针的第二键类型字段来指向更新的表的步骤。 提供了许多其他方面。
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公开(公告)号：US07411956B2
公开(公告)日：2008-08-12
申请号：US10454932
申请日：2003-06-05
IPC分类号： H04L12/28
CPC分类号： H04L45/54 , H04L45/02 , H04L45/742
摘要： In a first aspect, a first method is provided that includes the steps of (1) providing a pointer that includes a first keytype field and a second keytype field; and (2) assigning a value to the second keytype field of the pointer based on a tabletype field of an updated table. The updated table is an updated version of a first table written in a memory, and the first keytype field of the pointer has a value assigned based on a tabletype field of the first table. The first method further includes the step of employing the second keytype field of the pointer to point to the updated table. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了一种包括以下步骤的第一方法：（1）提供包括第一键类型字段和第二键类型字段的指针; 和（2）基于更新表的表格类型字段将值分配给指针的第二键类型字段。 更新的表是写入存储器的第一表的更新版本，并且指针的第一键类型字段具有基于第一表的表类型字段分配的值。 第一方法还包括采用指针的第二键类型字段来指向更新的表的步骤。 提供了许多其他方面。
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公开(公告)号：US08792332B2
公开(公告)日：2014-07-29
申请号：US12884389
申请日：2010-09-17
CPC分类号： H04L12/2602 , G06F11/0745 , G06F11/0793 , G06F13/4009 , H04L43/00 , H04W24/00 , H04W24/08 , H04W28/04
摘要： A method and circuit for implementing lane shuffle for fault-tolerant communication links, and a design structure on which the subject circuit resides are provided. Shuffle hardware logic steers a set of virtual data lanes onto a set of physical optical lanes, steering around all lanes that are detected as bad during link initialization training. A mask status register is loaded with a mask of lane fail information during link training, which flags the bad lanes, if any. The shuffle hardware logic uses a shift template, where each position in the starting template is a value representing the corresponding lane position. The shift template is cascaded through a set of shifters controlled by the fail mask.
摘要翻译： 一种用于实现用于容错通信链路的车道混洗的方法和电路，以及设置有该主题电路所在的设计结构。 随机的硬件逻辑将一组虚拟数据通道引导到一组物理光学通道上，在链路初始化训练期间绕着被检测为坏的所有通道转向。 在链路训练期间，掩码状态寄存器加载了通道故障信息的掩码，标志着不良通道（如果有的话）。 洗牌硬件逻辑使用移位模板，其中起始模板中的每个位置都是表示对应车道位置的值。 移位模板通过由失败掩码控制的一组移位器进行级联。
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9.发明授权公开(公告)号：US07961732B2
公开(公告)日：2011-06-14
申请号：US12044998
申请日：2008-03-09
IPC分类号： H04L12/28 , G06F15/167 , G06F15/173
CPC分类号： H04L69/12
摘要： A method and apparatus are provided for implementing frame alteration commands in a communications network processor. A set of frame alteration instruction templates is defined. A frame alteration instruction template is identified based upon the packet type recognition result of a received packet. A frame alteration instruction stream is generated utilizing the frame alteration instruction template. Each of the frame alteration instruction templates includes different frame alteration commands to be performed on a packet. Pointers to indirect data bytes to be inserted in a packet are stored in the frame alteration instruction templates. The generated frame alteration instruction stream is used by hardware to provide frame alterations.
摘要翻译： 提供了一种用于在通信网络处理器中实现帧改变命令的方法和装置。 定义了一组帧改变指令模板。 基于接收到的分组的分组类型识别结果来识别帧改变指令模板。 使用帧改变指令模板生成帧改变指令流。 每个帧改变指令模板包括要在分组上执行的不同帧改变命令。 要插入数据包的间接数据字节的指针存储在帧改变指令模板中。 生成的帧改变指令流被硬件用于提供帧改变。
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10.发明授权Method for implementing actions based on packet classification and lookup results 有权基于分组分类和查找结果实现动作的方法公开(公告)号：US07382777B2
公开(公告)日：2008-06-03
申请号：US10463288
申请日：2003-06-17
IPC分类号： H04L12/56 , G06F12/00 , G06F15/173
CPC分类号： H04L47/10 , H04L47/2408 , H04L47/2441
摘要： A method and apparatus are provided for implementing predefined actions based upon packet classification and lookup results in a communications network processor. A plurality of sets of rules is defined. Each rule set includes at least one rule and each rule has a set of masked compares for comparing results of hits and misses of table lookups. Each masked compare set has an associated field for selecting an action. The action defines a set of one or more commands and each command defines a processing operation. One rule set is identified based upon the packet classification result for a received packet. When one of the rules is identified having a match of the masked compares, then the action of associated with the identified rule is selected. Otherwise a default action is provided responsive to no rule of the identified rule set having a match of the masked compares.
摘要翻译： 提供了一种基于通信网络处理器中的分组分类和查找结果来实现预定动作的方法和装置。 定义了多组规则。 每个规则集包括至少一个规则，每个规则具有一组掩码的比较，用于比较表查找的命中和未命中的结果。 每个被屏蔽的比较集合都有一个关联的字段用于选择一个动作。 该动作定义一组一个或多个命令，每个命令定义一个处理操作。 基于接收到的分组的分组分类结果来识别一个规则集。 当识别出其中一个规则具有被掩蔽的比较的匹配时，则选择与所识别的规则相关联的动作。 否则，响应于不具有所掩蔽的比较的匹配的所识别的规则集的规则来提供默认动作。
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