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1.发明申请Using Extreme Data Rate Memory Commands to Scrub and Refresh Double Data Rate Memory 审中-公开使用极限数据速率存储器命令来刷新和刷新双倍数据速率存储器公开(公告)号：US20080183916A1
公开(公告)日：2008-07-31
申请号：US11668531
申请日：2007-01-30
申请人： Mark David Bellows , Paul Allen Ganfield , Ryan Abel Heckendorf , John David Irish , David Alan Norgaard , Ibrahim Abdel-Rahman Ouda , Tolga Ozguner
发明人： Mark David Bellows , Paul Allen Ganfield , Ryan Abel Heckendorf , John David Irish , David Alan Norgaard , Ibrahim Abdel-Rahman Ouda , Tolga Ozguner
IPC分类号： G06F13/00
CPC分类号： G06F11/106
摘要： In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a processor adapted to issue a command complying with a first protocol; (2) providing a memory coupled to the processor and accessible by a command complying with a second protocol; (3) employing a plurality of scrub commands complying with the second protocol to check respective portions of the memory for errors, wherein each scrub command complying with the second protocol is a converted version of a scrub command complying with the first protocol issued by the processor and the respective portions are non-sequential; and (4) refreshing bits stored in the entire memory within a predetermined time period. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）提供适于发出符合第一协议的命令的处理器; （2）提供耦合到所述处理器的存储器，并且可通过符合第二协议的命令来访问; （3）采用符合第二协议的多个擦除命令来检查存储器的相应部分的错误，其中符合第二协议的每个擦除命令是符合由处理器发出的第一协议的擦除命令的转换版本 并且各部分是非顺序的; 和（4）在预定时间段内刷新存储在整个存储器中的位。 提供了许多其他方面。
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2.发明申请公开(公告)号：US20080168298A1
公开(公告)日：2008-07-10
申请号：US11620104
申请日：2007-01-05
申请人： Mark David Bellows , Paul Allen Ganfield , David Alan Norgaard , Ibrahim Abdel-Rahman Ouda , Tolga Ozguner
发明人： Mark David Bellows , Paul Allen Ganfield , David Alan Norgaard , Ibrahim Abdel-Rahman Ouda , Tolga Ozguner
CPC分类号： G11C7/10 , G11C2207/2254
摘要： In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a computer system including (a) a memory; (b) a processor adapted to issue a functional command to the memory; (c) a translation chip; (d) a first link adapted to couple the processor to the translation chip; and (e) a second link adapted to couple the translation chip to the memory; (2) calibrating the first link using the translation chip; and (3) while calibrating the first link, calibrating the second link using the translation chip. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）提供一种包括（a）存储器的计算机系统; （b）适于向存储器发出功能命令的处理器; （c）翻译芯片; （d）适于将所述处理器耦合到所述翻译芯片的第一链接; 和（e）适于将所述翻译芯片耦合到所述存储器的第二链接; （2）使用翻译芯片校准第一链接; 和（3）在校准第一链路的同时，使用转换芯片校准第二链路。 提供了许多其他方面。
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3.发明申请Methods and Apparatus for Software Control of a Non-Functional Operation on Memory 审中-公开用于存储器中非功能操作的软件控制的方法和装置公开(公告)号：US20080168262A1
公开(公告)日：2008-07-10
申请号：US11620117
申请日：2007-01-05
申请人： Mark David Bellows , John David Irish , David Alan Norgaard , Tolga Ozguner , Dorothy Marie Thelen
发明人： Mark David Bellows , John David Irish , David Alan Norgaard , Tolga Ozguner , Dorothy Marie Thelen
IPC分类号： G06F9/312
CPC分类号： G06F9/3004
摘要： In a first aspect, a first method of controlling a non-functional operation on a memory of a computer system using software is provided. The first method includes the steps of (1) employing a processor to write bits of data to at least one register external to the processor, wherein the bits of data serve as control bits for the memory; and (2) applying the bits of data to respective pins of the memory so as to cause the non-functional operation to be performed on the memory. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了一种使用软件来控制计算机系统的存储器上的非功能操作的第一方法。 第一种方法包括以下步骤：（1）使用处理器将数据位写入到处理器外部的至少一个寄存器，其中数据位用作存储器的控制位; 以及（2）将数据位施加到存储器的相应引脚，以使得对存储器执行非功能性操作。 提供了许多其他方面。
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4.发明授权Rank select operation between an XIO interface and a double data rate interface 失效XIO接口和双数据速率接口之间的等级选择操作公开(公告)号：US07840744B2
公开(公告)日：2010-11-23
申请号：US11668725
申请日：2007-01-30
IPC分类号： G06F12/00
CPC分类号： G06F13/1694
摘要： In an aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) generating a first command and associated address of a first type that does not indicate a rank of memory targeted by the first command; (2) determining whether the memory includes a plurality of ranks; (3) if the memory includes a plurality of ranks, employing the processor to update the address associated with the first command to indicate a memory rank targeted by the first command; (4) if the memory does not include a plurality of ranks, employing the processor to update the address associated with the first command to indicate the memory does not include a plurality of ranks; and (5) converting the first command and associated updated address to a second command and associated address that are employed to access the memory. Numerous other aspects are provided.
摘要翻译： 在一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）生成不指示由第一命令指定的存储器的等级的第一类型的第一命令和相关联的地址; （2）确定存储器是否包括多个等级; （3）如果所述存储器包括多个等级，则使用所述处理器来更新与所述第一命令相关联的地址以指示由所述第一命令所针对的存储器级; （4）如果存储器不包括多个等级，则使用处理器来更新与第一命令相关联的地址以指示存储器不包括多个等级; 和（5）将第一命令和相关联的更新地址转换为用于访问存储器的第二命令和相关联的地址。 提供了许多其他方面。
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5.发明申请Rank Select Operation Between an XIO Interface and a Double Data Rate Interface 失效等级选择XIO接口和双数据速率接口之间的操作公开(公告)号：US20080183985A1
公开(公告)日：2008-07-31
申请号：US11668725
申请日：2007-01-30
IPC分类号： G06F12/00
CPC分类号： G06F13/1694
摘要： In an aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) generating a first command and associated address of a first type that does not indicate a rank of memory targeted by the first command; (2) determining whether the memory includes a plurality of ranks; (3) if the memory includes a plurality of ranks, employing the processor to update the address associated with the first command to indicate a memory rank targeted by the first command; (4) if the memory does not include a plurality of ranks, employing the processor to update the address associated with the first command to indicate the memory does not include a plurality of ranks; and (5) converting the first command and associated updated address to a second command and associated address that are employed to access the memory. Numerous other aspects are provided.
摘要翻译： 在一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）生成不指示由第一命令指定的存储器的等级的第一类型的第一命令和相关联的地址; （2）确定存储器是否包括多个等级; （3）如果所述存储器包括多个等级，则使用所述处理器来更新与所述第一命令相关联的地址以指示由所述第一命令所针对的存储器级; （4）如果存储器不包括多个等级，则使用处理器来更新与第一命令相关联的地址以指示存储器不包括多个等级; 和（5）将第一命令和相关联的更新地址转换为用于访问存储器的第二命令和相关联的地址。 提供了许多其他方面。
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公开(公告)号：US07317683B2
公开(公告)日：2008-01-08
申请号：US10015994
申请日：2001-11-01
IPC分类号： H04J1/16
CPC分类号： H04L49/30 , H04L47/2441 , H04L47/50 , H04L47/621 , H04L49/254
摘要： A data communication apparatus includes a plurality of output ports and a scheduler for assigning priorities for outbound data frames. The scheduler includes one or more scheduling queues. Each scheduling queue indicates an order in which data flows are to be serviced. At least one scheduling queue has a respective plurality of output ports assigned to the scheduling queue. That is, the scheduling queue is shared by two or more output ports.
摘要翻译： 数据通信装置包括多个输出端口和用于分配出站数据帧的优先级的调度器。 调度器包括一个或多个调度队列。 每个调度队列指示数据流被维护的顺序。 至少一个调度队列具有分配给调度队列的相应的多个输出端口。 也就是说，调度队列由两个或更多个输出端口共享。
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公开(公告)号：US07280474B2
公开(公告)日：2007-10-09
申请号：US10015760
申请日：2001-11-01
CPC分类号： H04L47/2441 , H04L47/36 , H04L47/50 , H04L47/623
摘要： A scheduler for a network processor includes a scheduling queue in which weighted fair queuing is applied. The scheduling queue has a range R. Flows are attached to the scheduling queue at a distance D from a current pointer for the scheduling queue. The distance D is calculated for each flow according to the formula D=((WF×FS)/SF), where WF is a weighting factor applicable to a respective flow; FS is a frame size attributable to the respective flow; and SF is a scaling factor. The scaling factor SF is adjusted depending on a comparison of the distance D to the range R.
摘要翻译： 网络处理器的调度器包括其中应用加权公平队列的调度队列。 调度队列具有范围R.流量与调度队列的当前指针距离D附加到调度队列。 根据公式D =（（WFxFS）/ SF）为每个流量计算距离D，其中WF是适用于相应流量的加权因子; FS是归因于相应流量的帧大小; SF是缩放因子。 根据距离D与范围R的比较来调整缩放因子SF。
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8.发明申请公开(公告)号：US20080159297A1
公开(公告)日：2008-07-03
申请号：US12044994
申请日：2008-03-09
IPC分类号： H04L12/56
CPC分类号： H04L47/50 , H04L2012/5679
摘要： A method and apparatus are provided for implementing hierarchical scheduling of oversubscribed virtual paths with underutilized bandwidth that works for both ATM (cell) and IP (frame) scheduling. A scheduler includes a first calendar for pipes and autonomous flows and a second calendar for pipe flows. A winner of a pipe or an autonomous flow is identified from the first calendar. Responsive to an identified winner pipe, a pipe queue is checked for an associated pipe flow for the winner pipe. Responsive to identifying an empty pipe queue for the winner pipe, a pipe win credit is assigned to the pipe without reattaching the winner pipe to the first calendar. Then a next winner is identified from the first calendar. When a winner pipe flow is identified from the second calendar and the pipe win credit is assigned to the pipe for the winner pipe flow, then the winner pipe flow is serviced without delay.
摘要翻译： 提供了一种方法和装置，用于实现对于ATM（小区）和IP（帧）调度工作的未充分利用的带宽的超额预订虚拟路径的分层调度。 调度器包括用于管道和自主流的第一日历和用于管道流的第二日历。 从第一个日历识别管道或自主流的获胜者。 对于确定的胜利者管道，检查管道队列以获得胜利管道的相关管道流量。 响应于为胜利者管道识别空管道队列，将管道赢取信用额度分配给管道，而不将胜利者管道重新连接到第一个日历。 然后从第一个日历识别下一个赢家。 当从第二个日历识别获胜者管道流量，并且将管道信贷分配给胜利者管道的管道时，优胜者管道流程将被无延误地维护。
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公开(公告)号：US07103051B2
公开(公告)日：2006-09-05
申请号：US10002416
申请日：2001-11-01
IPC分类号： H04L12/56
CPC分类号： H04L47/28 , H04L12/64 , H04L47/24 , H04L47/50 , H04L47/521 , H04L47/525 , H04L47/564 , H04L47/568
摘要： A scheduler, scheduling method, and computer program product are provided for implementing Quality-of-Service (QoS) scheduling of a plurality of flows with aging time stamps. Subsets of time stamp data stored in a time stamp aging memory array are sequentially accessed. Each time stamp data subset contains time stamp data for a subplurality of flows. Guaranteed aging processing steps are performed for each flow utilizing the time stamp data subsets to identify and mark invalid calendar next time values. When a new frame arrival for an empty flow is identified, flow queue control block (FQCB) time stamp data and the flow time stamp data in the time stamp aging memory array are accessed. Based on the calendar to which the new frame is directed or the target calendar for the new frame, the target calendar next time valid bit of the time stamp aging memory array data is checked. When the target calendar next time valid bit is on, a target calendar next time value from the flow queue control block (FQCB) time stamp data is compared with a current time. When the target calendar next time is less than the current time, the target calendar next time valid bit is turned off to mark the target calendar next time as invalid. The guaranteed aging processing steps for each flow in the time stamp data subset includes checking a selection indicator of the time stamp aging memory array data for the flow to identify a calendar. Responsive to the selection indicator value, a calendar valid bit is checked. When the calendar valid bit is on, a calendar next time is compared with a current time. When the calendar next time is less than the current time, the calendar valid bit is turned off to mark the calendar next time as invalid. Invalid time stamp values are identified for all scheduler calendars.
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10.发明授权Method and apparatus for improving the fairness of new attaches to a weighted fair queue in a quality of service (QoS) scheduler 失效用于提高服务质量（QoS）调度器中的加权公平队列的新附加的公平性的方法和装置公开(公告)号：US07257124B2
公开(公告)日：2007-08-14
申请号：US10102166
申请日：2002-03-20
CPC分类号： H04L47/10 , H04L47/2441
摘要： In a first aspect, a network processor includes a scheduler in which a scheduling queue is maintained. A last frame is dispatched from a flow queue maintained in the network processor, thereby emptying the flow queue. Data indicative of the size of the dispatched last frame is stored in association with the scheduler. A new frame corresponding to the emptied flow queue is received, and the flow corresponding to the emptied flow queue is attached to the scheduling queue. The flow is attached to the scheduling queue at a distance D from a current pointer for the scheduling queue. The distance D is determined based at least in part on the stored data indicative of the size of the dispatched last frame.
摘要翻译： 在第一方面，网络处理器包括维护调度队列的调度器。 从网络处理器中维护的流队列调度最后一帧，从而清空流队列。 指示调度的最后一帧的大小的数据与调度器相关联地存储。 接收到与排空流队列对应的新帧，将与排空流队列对应的流附加到调度队列。 该流程与调度队列的当前指针距离D附加到调度队列。 至少部分地基于存储的指示调度的最后帧的大小的数据来确定距离D.
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