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公开(公告)号：US07047350B2
公开(公告)日：2006-05-16
申请号：US10683778
申请日：2003-10-10
IPC分类号： G06F13/00
CPC分类号： G06F13/4027 , Y02D10/14 , Y02D10/151
摘要： A data processing system (30) includes two processors (70, 80) and a serial data controller (36) for selectively multiplexing serial data signals between one or more of a plurality of serial data devices (40, 42, 44, 46, 74, 76, 82) The serial data controller (36) includes one or more host ports (50, 52, 54) and one or more peripheral ports (56, 58, 60, 62) coupled together through a switching matrix (64). A control circuit (66) and a plurality of control registers (68) are used to configure and control a serial data path created between two or more ports including clock and frame synchronization timing of the data path.
摘要翻译： 数据处理系统（30）包括两个处理器（70,80）和串行数据控制器（36），用于在多个串行数据设备（40,42,44,46,74）中的一个或多个串行数据设备 串行数据控制器（36）包括通过交换矩阵（64）耦合在一起的一个或多个主机端口（50,52,54）和一个或多个外围端口（56,58,60,62）。 控制电路（66）和多个控制寄存器（68）用于配置和控制在包括数据路径的时钟和帧同步定时的两个或多个端口之间创建的串行数据路径。
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公开(公告)号：US20120183029A1
公开(公告)日：2012-07-19
申请号：US13366347
申请日：2012-02-05
申请人： John J. Vaglica , Christopher K. Y. Chun , Jose G. Corleto-Mena , Arnaldo R. Cruz , Jianping Tao , Mieu V. Vu , Mark E. Elledge , Charbel Khawand , Arthur M. Goldberg , David J. Hayes
发明人： John J. Vaglica , Christopher K. Y. Chun , Jose G. Corleto-Mena , Arnaldo R. Cruz , Jianping Tao , Mieu V. Vu , Mark E. Elledge , Charbel Khawand , Arthur M. Goldberg , David J. Hayes
IPC分类号： H04B1/38
CPC分类号： H04W84/08
摘要： A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times
摘要翻译： 包括调制解调器处理器和存储器的蜂窝移动站。 存储器包括用于调制解调器处理器执行第1层处理器操作，第2层处理器操作和第3层处理器操作的指令。 调制解调器处理器执行指令，以便根据蜂窝通信协议对蜂窝移动站执行通信数据的处理器操作。 在一个示例中，移动站包括不同级别的存储器以提供不同的确定性访问时间
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公开(公告)号：US09198224B2
公开(公告)日：2015-11-24
申请号：US13366347
申请日：2012-02-05
申请人： John J. Vaglica , Christopher K. Y. Chun , Jose G. Corleto-Mena , Arnaldo R. Cruz , Jianping Tao , Mieu V. Vu , Mark E. Elledge , Charbel Khawand , Arthur M. Goldberg , David J. Hayes
发明人： John J. Vaglica , Christopher K. Y. Chun , Jose G. Corleto-Mena , Arnaldo R. Cruz , Jianping Tao , Mieu V. Vu , Mark E. Elledge , Charbel Khawand , Arthur M. Goldberg , David J. Hayes
CPC分类号： H04W84/08
摘要： A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times.
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公开(公告)号：US08131316B2
公开(公告)日：2012-03-06
申请号：US12606044
申请日：2009-10-26
申请人： John J. Vaglica , Christopher K. Y. Chun , Jose G. Corleto-Mena , Arnaldo R. Cruz , Jianping Tao , Mieu V. Vu , Mark E. Elledge , Charbel Khawand , Arthur M. Goldberg , David J. Hayes
发明人： John J. Vaglica , Christopher K. Y. Chun , Jose G. Corleto-Mena , Arnaldo R. Cruz , Jianping Tao , Mieu V. Vu , Mark E. Elledge , Charbel Khawand , Arthur M. Goldberg , David J. Hayes
CPC分类号： H04W84/08
摘要： A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times.
摘要翻译： 包括调制解调器处理器和存储器的蜂窝移动站。 存储器包括用于调制解调器处理器执行第1层处理器操作，第2层处理器操作和第3层处理器操作的指令。 调制解调器处理器执行指令，以便根据蜂窝通信协议对蜂窝移动站执行通信数据的处理器操作。 在一个示例中，移动站包括不同级别的存储器以提供不同的确定性访问时间。
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公开(公告)号：US07623894B2
公开(公告)日：2009-11-24
申请号：US10682746
申请日：2003-10-09
申请人： John J. Vaglica , Christopher K. Y. Chun , Jose G. Corleto-Mena , Arnaldo R. Cruz , Jianping Tao , Mieu V. Vu , Mark E. Elledge , Charbel Khawand , Arthur M. Goldberg , David J. Hayes
发明人： John J. Vaglica , Christopher K. Y. Chun , Jose G. Corleto-Mena , Arnaldo R. Cruz , Jianping Tao , Mieu V. Vu , Mark E. Elledge , Charbel Khawand , Arthur M. Goldberg , David J. Hayes
CPC分类号： H04W84/08
摘要： A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times.
摘要翻译： 包括调制解调器处理器和存储器的蜂窝移动站。 存储器包括用于调制解调器处理器执行第1层处理器操作，第2层处理器操作和第3层处理器操作的指令。 调制解调器处理器执行指令，以便根据蜂窝通信协议对蜂窝移动站执行通信数据的处理器操作。 在一个示例中，移动站包括不同级别的存储器以提供不同的确定性访问时间。
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公开(公告)号：US08332641B2
公开(公告)日：2012-12-11
申请号：US12363259
申请日：2009-01-30
申请人： Lawrence L. Case , Asaf Ashkenazi , Ruchir Chhabra , Carlin R. Covey , David H. Hartley , Troy E. Mackie , Alistair N. Muir , Mark D. Redman , Thomas E. Tkacik , John J. Vaglica , Rodney D. Ziolkowski
发明人： Lawrence L. Case , Asaf Ashkenazi , Ruchir Chhabra , Carlin R. Covey , David H. Hartley , Troy E. Mackie , Alistair N. Muir , Mark D. Redman , Thomas E. Tkacik , John J. Vaglica , Rodney D. Ziolkowski
IPC分类号： G06F9/00
CPC分类号： G06F11/3656 , H04L9/3247 , H04L9/3271
摘要： Under the direction of a first party, an integrated circuit (IC) device is configured to temporarily enable access to a debug interface of the IC device via authentication of the first party by a challenge/response process using a key of the IC device and a challenge value generated at the IC device. The first party then may conduct a software evaluation of the IC device via the debug interface. In response to failing to identify an issue with the IC device from the software evaluation, the first party can permanently enable open access to the debug interface while authenticated and provide the IC device to a second party. Under the direction of the second party, a hardware evaluation of the IC device is conducted via the debug interface that was permanently opened by the first party.
摘要翻译： 在第一方的指导下，集成电路（IC）装置被配置为通过使用IC装置的密钥的询问/响应处理来暂时使能通过第一方的认证访问IC设备的调试接口，以及 在IC器件产生的挑战值。 第一方然后可以通过调试接口对IC设备进行软件评估。 响应于从软件评估中未能识别IC设备的问题，第一方可以在认证时永久地启用对调试接口的开放访问，并将IC设备提供给第二方。 在第二方的指导下，通过由第一方永久打开的调试接口进行IC设备的硬件评估。
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公开(公告)号：US20100199077A1
公开(公告)日：2010-08-05
申请号：US12363259
申请日：2009-01-30
申请人： Lawrence L. Case , Asaf Ashkenazi , Ruchir Chhabra , Carlin R. Covey , David H. Hartley , Troy E. Mackie , Alistair N. Muir , Mark D. Redman , Thomas E. Tkacik , John J. Vaglica , Rodney D. Ziolkowski
发明人： Lawrence L. Case , Asaf Ashkenazi , Ruchir Chhabra , Carlin R. Covey , David H. Hartley , Troy E. Mackie , Alistair N. Muir , Mark D. Redman , Thomas E. Tkacik , John J. Vaglica , Rodney D. Ziolkowski
CPC分类号： G06F11/3656 , H04L9/3247 , H04L9/3271
摘要： Under the direction of a first party, an integrated circuit (IC) device is configured to temporarily enable access to a debug interface of the IC device via authentication of the first party by a challenge/response process using a key of the IC device and a challenge value generated at the IC device. The first party then may conduct a software evaluation of the IC device via the debug interface. In response to failing to identify an issue with the IC device from the software evaluation, the first party can permanently enable open access to the debug interface while authenticated and provide the IC device to a second party. Under the direction of the second party, a hardware evaluation of the IC device is conducted via the debug interface that was permanently opened by the first party.
摘要翻译： 在第一方的指导下，集成电路（IC）装置被配置为通过使用IC装置的密钥的询问/响应处理来暂时使能通过第一方的认证访问IC设备的调试接口，以及 在IC器件产生的挑战值。 第一方然后可以通过调试接口对IC设备进行软件评估。 响应于从软件评估中未能识别IC设备的问题，第一方可以在认证时永久地启用对调试接口的打开访问，并将IC设备提供给第二方。 在第二方的指导下，通过由第一方永久打开的调试接口进行IC设备的硬件评估。
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8.发明授权Method and apparatus for responding to access errors in a data processing system 有权用于在数据处理系统中响应访问错误的方法和装置公开(公告)号：US07278062B2
公开(公告)日：2007-10-02
申请号：US10339022
申请日：2003-01-09
IPC分类号： G06F11/00
CPC分类号： G06F11/004 , G06F11/0745 , G06F11/0751 , G06F11/0793
摘要： In one embodiment, a data processing system (10) has a processor (14) coupled to a bus, where the data processing system (10) includes access error detection circuitry (26) and access error response circuitry (12), each coupled to the bus (58, 60). The access error detection circuitry detects an access error in the data processing system. The access error response circuitry initiates replacement of an existing value on the bus with a predetermined value when the access error has been detected, and continues to replace the existing value on the bus with the predetermined value when the access error has been detected and a persistent mode indicator has been asserted. The predetermined value may correspond to a predetermined instruction value (74) or a predetermined data value (76). In one embodiment, different values for the predetermined value may be used depending on the current operating mode of the data processing system.
摘要翻译： 在一个实施例中，数据处理系统（10）具有耦合到总线的处理器（14），其中数据处理系统（10）包括访问错误检测电路（26）和访问错误响应电路（12），每个耦合到 公共汽车（58,60）。 访问错误检测电路检测数据处理系统中的访问错误。 当检测到访问错误时，访问错误响应电路以预定值启动总线上的现有值的替换，并且当已经检测到访问错误时，继续以预定值替换总线上的现有值，并且持续 模式指示器已被断言。 预定值可以对应于预定指令值（74）或预定数据值（76）。 在一个实施例中，可以根据数据处理系统的当前操作模式使用预定值的不同值。
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公开(公告)号：US4942522A
公开(公告)日：1990-07-17
申请号：US234103
申请日：1988-08-19
摘要： A timer channel with multiple timer reference signals available to it which is capable of performing any input or output timer function with reference to any of the available reference signals. In addition, input timer functions may be related to the occurrence of output functions. For instance, the state of one timer reference may be captured automatically at a specified time referenced to another timer reference. Another feature of the invention provides for the creation of a time-out window for an input timer function through the use of a concurrent output function.
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10.发明授权Integrated circuit timer with multiple channels and dedicated service processor 失效多通道集成电路定时器和专用服务处理器
公开(公告)号：US4926319A
公开(公告)日：1990-05-15
申请号：US234104
申请日：1988-08-19
IPC分类号： G04G3/00 , G04G99/00 , G06F1/14 , G06F15/16 , G06F15/177
摘要： A timer system comprises multiple channels, each of which is capable of performing input and output timer functions referenced to any of a plurality of timer reference signals. In the preferred embodiment, sixteen independent channels are serviced by a processor dedicated to that purpose and each can perform capture and match functions referenced to either of two free-running counters.
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