公开(公告)号：US20090217009A1

公开(公告)日：2009-08-27

申请号：US12036520

申请日：2008-02-25

申请人： Chung-Lung Kevin Shum ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Bruce C. Giamei ,  Bernd Nerz ,  David A. Schroter ,  Charles F. Webb

发明人： Chung-Lung Kevin Shum ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Bruce C. Giamei ,  Bernd Nerz ,  David A. Schroter ,  Charles F. Webb

IPC分类号： G06F9/318

CPC分类号： G06F9/3017 ,  G06F9/30018 ,  G06F9/30101 ,  G06F9/355

摘要： A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.

摘要翻译： 一种用于计算机系统中的翻译的系统，方法和计算机程序产品。 该系统包括包含地址转换表的基地址的通用寄存器。 该系统还包括被配置为接收多个要被翻译的元件的毫代可访问特殊位移寄存器。 该系统还包括多路复用器，用于从毫代可访问特殊位移寄存器中选择多个元件中的特定元件，并用于产生位移或偏移值。 该系统还包括地址发生器，用于创建包含来自通用寄存器的基地址和所生成的位移或偏移值的组合地址。

公开(公告)号：US08176301B2

公开(公告)日：2012-05-08

申请号：US12031756

申请日：2008-02-15

申请人： Mark S. Farrell ,  Bruce C. Giamei ,  Chung-Lung Kevin Shum

发明人： Mark S. Farrell ,  Bruce C. Giamei ,  Chung-Lung Kevin Shum

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC分类号： G06F9/3017 ,  G06F9/30003 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/3824 ,  G06F9/3861

摘要： Millicode store access checking instructions are provided via an operand access control register (OACR) including a test modifier indicator, which is communicatively coupled to an instruction unit subsystem, the instruction unit subsystem for fetching and decoding instructions. The instructions include a millicode instruction with an operand defining an address to check for a store access exception. In addition, an execution unit for executing the millicode instruction performs a method. The method includes receiving the millicode instruction from the instruction unit subsystem, testing for the store access exception at the address as if the test modifier is set absent an update to the OACR, and outputting a result of the testing for the store access exception.

摘要翻译： 经由操作数访问控制寄存器（OACR）提供Millicode存储访问检查指令，该操作数访问控制寄存器（OACR）包括通信地耦合到指令单元子系统的指令单元子系统，用于获取和解码指令。 该指令包括一个具有操作数的millicode指令，其中定义了一个地址来检查存储访问异常。 另外，用于执行millicode指令的执行单元执行一种方法。 该方法包括从指令单元子系统接收millicode指令，测试地址处的存储访问异常，就好像将测试修饰符设置为不存在对OACR的更新，并输出用于存储访问异常的测试结果。

公开(公告)号：US07966474B2

公开(公告)日：2011-06-21

申请号：US12036520

申请日：2008-02-25

申请人： Chung-Lung Kevin Shum ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Bruce C Giamei ,  Bernd Nerz ,  David A. Schroter ,  Charles F. Webb

发明人： Chung-Lung Kevin Shum ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Bruce C Giamei ,  Bernd Nerz ,  David A. Schroter ,  Charles F. Webb

IPC分类号： G06F9/26

CPC分类号： G06F9/3017 ,  G06F9/30018 ,  G06F9/30101 ,  G06F9/355

摘要： A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.

摘要翻译： 一种用于计算机系统中的翻译的系统，方法和计算机程序产品。 该系统包括包含地址转换表的基地址的通用寄存器。 该系统还包括被配置为接收多个要被翻译的元件的毫代可访问特殊位移寄存器。 该系统还包括多路复用器，用于从毫代可访问特殊位移寄存器中选择多个元件中的特定元件，并用于产生位移或偏移值。 该系统还包括地址发生器，用于创建包含来自通用寄存器的基地址和所生成的位移或偏移值的组合地址。

公开(公告)号：US20090210680A1

公开(公告)日：2009-08-20

申请号：US12031756

申请日：2008-02-15

申请人： Mark S. Farrell ,  Bruce C. Giamei ,  Chung-Lung Kevin Shum

发明人： Mark S. Farrell ,  Bruce C. Giamei ,  Chung-Lung Kevin Shum

IPC分类号： G06F9/30

CPC分类号： G06F9/3017 ,  G06F9/30003 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/3824 ,  G06F9/3861

摘要： A system, method and computer program product for a millicode store access checking instruction are provided. The system includes an operand access control register (OACR) including a test modifier indicator. The system also includes an instruction unit subsystem for fetching and decoding instructions. The instructions include a millicode instruction with an operand defining an address to check for a store access exception. The system further includes an execution unit to execute the millicode instruction. The execution unit performs a method. The method includes receiving the millicode instruction from the instruction unit subsystem, testing for the store access exception at the address as if the test modifier is set absent an update to the OACR, and outputting a result of the testing for the store access exception.

摘要翻译： 提供了一种用于毫存储存储访问检查指令的系统，方法和计算机程序产品。 该系统包括一个操作数访问控制寄存器（OACR），包括一个测试修改器指示符。 该系统还包括用于获取和解码指令的指令单元子系统。 该指令包括一个具有操作数的millicode指令，其中定义了一个地址来检查存储访问异常。 该系统还包括执行毫代码指令的执行单元。 执行单元执行方法。 该方法包括从指令单元子系统接收millicode指令，测试地址处的存储访问异常，就好像将测试修饰符设置为不存在对OACR的更新，并输出用于存储访问异常的测试结果。

公开(公告)号：US20090240922A1

公开(公告)日：2009-09-24

申请号：US12051792

申请日：2008-03-19

申请人： David S. Hutton ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Christopher A. Krygowski ,  Edward T. Malley ,  Jeffrey S. Plate ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum ,  Timothy J. Slegel

发明人： David S. Hutton ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Christopher A. Krygowski ,  Edward T. Malley ,  Jeffrey S. Plate ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum ,  Timothy J. Slegel

IPC分类号： G06F9/30

CPC分类号： G06F9/3016 ,  G06F9/30036 ,  G06F9/3828

摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.

摘要翻译： 通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令 以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发， 因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。

公开(公告)号：US07861064B2

公开(公告)日：2010-12-28

申请号：US12037861

申请日：2008-02-26

申请人： Khary J. Alexander ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  David S. Hutton ,  Chung-Lung Kevin Shum

发明人： Khary J. Alexander ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  David S. Hutton ,  Chung-Lung Kevin Shum

IPC分类号： G06F9/34 ,  G06F9/38

CPC分类号： G06F9/3826 ,  G06F9/3836

摘要： A method for selectively accelerating early instruction processing including receiving an instruction data that is normally processed in an execution stage of a processor pipeline, wherein a configuration of the instruction data allows a processing of the instruction data to be accelerated from the execution stage to an address generation stage that occurs earlier in the processor pipeline than the execution stage, determining whether the instruction data can be dispatched to the address generation stage to be processed without being delayed due to an unavailability of a processing resource needed for the processing of the instruction data in the address generation stage, dispatching the instruction data to be processed in the address generation stage if it can be dispatched without being delayed due to the unavailability of the processing resource, and dispatching the instruction data to be processed in the execution stage if it can not be dispatched without being delayed due to the unavailability of the processing resource, wherein the processing of the instruction data is selectively accelerated using an address generation interlock scheme. A corresponding system and computer program product.

摘要翻译： 一种用于选择性地加速早期指令处理的方法，包括接收在处理器流水线的执行阶段中正常处理的指令数据，其中指令数据的配置允许指令数据的处理从执行阶段加速到地址 在处理器流水线中比执行阶段更早发生的生成阶段，确定指令数据是否可以被分派到要处理的地址生成阶段，而不会由于处理指令数据所需的处理资源的不可用而被延迟 地址生成阶段，如果能够由于处理资源的不可用而被分派而不被延迟，则在地址生成阶段调度要处理的指令数据，并且如果不能在执行阶段调度要处理的指令数据 由于你而不被推迟 处理资源的可用性，其中使用地址生成互锁方案选择性地加速指令数据的处理。 相应的系统和计算机程序产品。

公开(公告)号：US07975130B2

公开(公告)日：2011-07-05

申请号：US12034042

申请日：2008-02-20

申请人： Khary J. Alexander ,  Fadi Y. Busada ,  Bruce C. Giamei ,  David S. Hutton ,  Chung-Lung Kevin Shum

发明人： Khary J. Alexander ,  Fadi Y. Busada ,  Bruce C. Giamei ,  David S. Hutton ,  Chung-Lung Kevin Shum

IPC分类号： G06F9/312

CPC分类号： G06F9/3826 ,  G06F9/3016 ,  G06F9/382 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3861

摘要： A method and system for early instruction text based operand store compare avoidance in a processor are provided. The system includes a processor pipeline for processing instruction text in an instruction stream, where the instruction text includes operand address information. The system also includes delay logic to monitor the instruction stream. The delay logic performs a method that includes detecting a load instruction following a store instruction in the instruction stream, comparing the operand address information of the store instruction with the load instruction. The method also includes delaying the load instruction in the processor pipeline in response to detecting a common field value between the operand address information of the store instruction and the load instruction.

摘要翻译： 提供了一种用于处理器中早期指令文本操作数存储比较避免的方法和系统。 该系统包括用于处理指令流中的指令文本的处理器流水线，其中指令文本包括操作数地址信息。 该系统还包括监视指令流的延迟逻辑。 延迟逻辑执行一种方法，其包括检测在指令流中的存储指令之后的加载指令，将存储指令的操作数地址信息与加载指令进行比较。 响应于检测存储指令的操作数地址信息和加载指令之间的公共字段值，该方法还包括延迟处理器流水线中的加载指令。

公开(公告)号：US20090210656A1

公开(公告)日：2009-08-20

申请号：US12034084

申请日：2008-02-20

申请人： David S. Hutton ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  John G. Rell, JR. ,  Eric M. Schwarz ,  Chung-Lung Kevin Shum

发明人： David S. Hutton ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  John G. Rell, JR. ,  Eric M. Schwarz ,  Chung-Lung Kevin Shum

IPC分类号： G06F15/76 ,  G06F9/02 ,  G06F9/312

CPC分类号： G06F9/3836 ,  G06F9/3857 ,  G06F9/3873

摘要： A system and method for overlapping execution (OE) of instructions through non-uniform execution pipelines in an in-order processor are provided. The system includes a first execution unit to perform instruction execution in a first execution pipeline. The system also includes a second execution unit to perform instruction execution in a second execution pipeline, where the second execution pipeline includes a greater number of stages than the first execution pipeline. The system further includes an instruction dispatch unit (IDU), the IDU including OE registers and logic for dispatching an OE-capable instruction to the first execution unit such that the instruction completes execution prior to completing execution of a previously dispatched instruction to the second execution unit. The system additionally includes a latch to hold a result of the execution of the OE-capable instruction until after the second execution unit completes the execution of the previously dispatched instruction.

摘要翻译： 提供了一种用于通过在顺序处理器中的非均匀执行管线来重复执行（OE）指令的系统和方法。 该系统包括在第一执行流水线中执行指令执行的第一执行单元。 该系统还包括第二执行单元，用于在第二执行流水线中执行指令执行，其中第二执行流水线包括比第一执行流水线更多的级数。 该系统还包括一个指令调度单元（IDU），该IDU包括OE寄存器和用于向第一执行单元分配一个OE能力指令的逻辑，使得指令在完成先前发送的指令执行之前完成执行 单元。 该系统还包括一个锁存器，用于保持执行OE能力指令的结果，直到第二执行单元完成先前发送的指令的执行。

公开(公告)号：US09164761B2

公开(公告)日：2015-10-20

申请号：US12033351

申请日：2008-02-19

申请人： Aaron Tsai ,  Bruce C. Giamei ,  Chung-Lung Kevin Shum ,  Scott B. Swaney

发明人： Aaron Tsai ,  Bruce C. Giamei ,  Chung-Lung Kevin Shum ,  Scott B. Swaney

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30032 ,  G06F9/30101 ,  G06F9/3879

摘要： A pipelined processor including one or more units having storage locations not directly accessible by software instructions. The processor includes a load-store unit (LSU) in direct communication with the one or more units for accessing the storage locations in response to special instructions. The processor also includes a requesting unit for receiving a special instruction from a requestor and a mechanism for performing a method. The method includes broadcasting storage location information from the special instruction to one or more of the units to determine a corresponding unit having the storage location specified by the special instruction. Execution of the special instruction is initiated at the corresponding unit. If the unit executing the special instruction is not the LSU, the data is sent to the LSU. The data is received from the LSU as a result of the execution of the special instruction. The data is provided to the requester.

摘要翻译： 流水线处理器包括一个或多个单元，其具有不能由软件指令直接访问的存储位置。 处理器包括与一个或多个单元直接通信的加载存储单元（LSU），用于响应于特殊指令访问存储位置。 处理器还包括用于从请求者接收特殊指令的请求单元和用于执行方法的机制。 该方法包括将特定指令中的存储位置信息广播到一个或多个单元，以确定具有由特殊指令指定的存储位置的对应单元。 特殊指令的执行在相应的单位启动。 如果执行特殊指令的单元不是LSU，则将数据发送到LSU。 作为执行特殊指令的结果，从LSU接收数据。 数据被提供给请求者。

公开(公告)号：US07921279B2

公开(公告)日：2011-04-05

申请号：US12051792

申请日：2008-03-19

申请人： David S. Hutton ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Christopher A. Krygowski ,  Edward T. Malley ,  Jeffrey S. Plate ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum ,  Timothy J. Slegel

发明人： David S. Hutton ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Christopher A. Krygowski ,  Edward T. Malley ,  Jeffrey S. Plate ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum ,  Timothy J. Slegel

IPC分类号： G06F9/30

CPC分类号： G06F9/3016 ,  G06F9/30036 ,  G06F9/3828

摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.

摘要翻译： 通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令 以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发， 因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。