公开(公告)号：US07173842B2

公开(公告)日：2007-02-06

申请号：US10816260

申请日：2004-03-31

申请人： Mark S. Isenberger ,  Hitesh Windlass ,  Wayne K. Ford ,  Carlton E Hanna

发明人： Mark S. Isenberger ,  Hitesh Windlass ,  Wayne K. Ford ,  Carlton E Hanna

IPC分类号： G11C11/22

CPC分类号： H01L23/345 ,  G11C11/22 ,  H01L27/11502 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of the invention provides an on-chip heating system to both initially anneal and revive cycle-fatigued polymer ferroelectric materials utilized in memory devices. By heating the polymer ferroelectric material above its Curie temperature, the polymer ferroelectric material can crystallize as it cools. As such, the ferroelectric properties of the polymer are enhanced and/or restored.

摘要翻译： 本发明的一个实施例提供一种片上加热系统，用于初始退火和恢复在存储器件中使用的循环疲劳的聚合物铁电材料。 通过将聚合物铁电材料加热到高于其居里温度，聚合物铁电材料可以在其冷却时结晶。 因此，提高和/或恢复聚合物的铁电性能。

公开(公告)号：US07084446B2

公开(公告)日：2006-08-01

申请号：US10648538

申请日：2003-08-25

申请人： Mark S. Isenberger

发明人： Mark S. Isenberger

IPC分类号： H01L29/94

CPC分类号： G11C11/22

摘要： A polymer memory and its method of manufacture are provided. One multi-layer construction of the polymer memory has two sets of word lines and a set of bit lines between the word lines. The word lines of each set of word lines have center lines that are spaced by a first distance from one another, and the bit lines have center lines spaced by a second distance from one another, the second distance being less than the first distance. Three masking steps are required to manufacture the three layers of lines. Older-technology machinery and masks are used to form the two layers of word lines, and new-technology machinery and masks are used to manufacture the bit lines. As such, only 33% of the machinery has to be upgraded for manufacturing one multi-layer construction. The entire polymer memory has four multi-layer constructions having a total of 12 layers of lines, of which four layers require new-technology machinery. The multi-layer constructions are formed on underlying electronics. The underlying electronics are constructed utilizing 28 masking steps, 4 of the 28 masking steps requiring new-technology machinery. As such, the manufacture of the entire polymer memory requires 40 masking steps, 8 of which require new-technology machinery. A 20% machinery upgrade is thus required for manufacturing the entire polymer memory, which is generally regarded as acceptable when upgrading machinery from one generation to the next.

摘要翻译： 提供聚合物记忆及其制造方法。 聚合物存储器的一个多层结构具有两组字线和字线之间的一组位线。 每组字线的字线具有彼此隔开第一距离的中心线，并且位线具有彼此隔开第二距离的中心线，第二距离小于第一距离。 需要三个掩蔽步骤来制造三层线。 旧技术机械和掩模用于形成两层字线，新技术机械和掩模用于制造位线。 因此，只有33％的机械必须升级制造一个多层建筑。 整个聚合物存储器具有四个多层结构，共有12层线，其中四层需要新技术的机械。 多层结构形成在底层电子设备上。 底层电子设备采用28个屏蔽步骤，28个屏蔽步骤中的4个需要新技术机械。 因此，整个聚合物记忆体的制造需要40个掩模步骤，其中8个需要新技术的机械。 因此，制造整个聚合物记忆体需要20％的机械升级，在将机器从一代升级到下一代时通常被认为是可接受的。

公开(公告)号：US07407819B2

公开(公告)日：2008-08-05

申请号：US11436209

申请日：2006-05-17

申请人： Mark S. Isenberger

发明人： Mark S. Isenberger

IPC分类号： H01L21/82 ,  H01L31/119

CPC分类号： G11C11/22

摘要： A polymer memory and its method of manufacture are provided. One multi-layer construction of the polymer memory has two sets of word lines and a set of bit lines between the word lines. The word lines of each set of word lines have center lines that are spaced by a first distance from one another, and the bit lines have center lines spaced by a second distance from one another, the second distance being less than the first distance. Three masking steps are required to manufacture the three layers of lines. Older-technology machinery and masks are used to form the two layers of word lines, and new-technology machinery and masks are used to manufacture the bit lines.

摘要翻译： 提供聚合物记忆及其制造方法。 聚合物存储器的一个多层结构具有两组字线和字线之间的一组位线。 每组字线的字线具有彼此隔开第一距离的中心线，并且位线具有彼此隔开第二距离的中心线，第二距离小于第一距离。 需要三个掩蔽步骤来制造三层线。 旧技术机械和掩模用于形成两层字线，新技术机械和掩模用于制造位线。

公开(公告)号：US07164166B2

公开(公告)日：2007-01-16

申请号：US10804795

申请日：2004-03-19

申请人： Mark S. Isenberger ,  Ebrahim Andideh

发明人： Mark S. Isenberger ,  Ebrahim Andideh

IPC分类号： H01L29/76

CPC分类号： H01L27/11585 ,  H01L27/115 ,  H01L27/1159 ,  H01L29/78391

摘要： A memory circuit is provided with a spacer formed on a support surface and positioned adjacent to a first electrode surface of a first electrode. The memory circuit further includes a ferroelectric layer formed on the first electrode and the spacer.

摘要翻译： 存储器电路设置有形成在支撑表面上并且邻近第一电极的第一电极表面定位的间隔件。 存储电路还包括形成在第一电极和间隔物上的铁电层。