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1.发明授权公开(公告)号：US07200153B2
公开(公告)日：2007-04-03
申请号：US09960007
申请日：2001-09-20
CPC分类号： H03L7/06 , H04L7/0004 , H04L7/02 , H04L7/0337 , H04L12/40169 , H04L49/3054
摘要： An apparatus and method for automatically detecting the port type of a remote device are disclosed. One embodiment of the apparatus includes a data rate detection unit to sample a data rate from an incoming data signal. A first frequency configuration unit is operatively coupled with the data rate detection unit to receive a detected data rate from the data rate detection unit. The apparatus also includes an oscillator to generate a plurality of reference clock frequencies. A frequency selector unit is coupled with the oscillator to select one of the reference clock frequencies. A phase lock unit to phase lock the incoming data signal is coupled with the first frequency configuration unit. A data rate select output is coupled with the first frequency configuration unit to operatively link the first frequency configuration unit with a second frequency configuration unit of a remote device.
摘要翻译： 公开了一种用于自动检测远程设备的端口类型的设备和方法。 该装置的一个实施例包括数据速率检测单元，用于从输入数据信号中采样数据速率。 第一频率配置单元与数据速率检测单元可操作地耦合以从数据速率检测单元接收检测到的数据速率。 该装置还包括产生多个参考时钟频率的振荡器。 频率选择器单元与振荡器耦合以选择参考时钟频率之一。 锁定输入数据信号的锁相单元与第一频率配置单元耦合。 数据速率选择输出与第一频率配置单元耦合，以将第一频率配置单元与远程设备的第二频率配置单元可操作地连接。
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公开(公告)号：US06956922B2
公开(公告)日：2005-10-18
申请号：US09968407
申请日：2001-09-28
申请人： Paul J. Weldon , Henning Lysdal
发明人： Paul J. Weldon , Henning Lysdal
摘要： A clock divider and method is disclosed for generating an output clock signal having a frequency that is a fractional or integral multiple of a reference clock signal frequency. In one embodiment, the clock divider divides a clock signal by a first divisor in a first period and by a second divisor in a second period, where the second period following the first period. The clock divider circuit is triggered by a first edge of the clock signal and generates a first signal. A synchronizing circuit is coupled to the clock divider to generate a second signal from the first signal, the second signal being synchronized by a second edge of the clock signal, where the second edge is in a direction opposite to the first edge. A selector is coupled to the synchronizing circuit and the clock divider to generate an output signal by selecting the first signal and the second signal alternately between the first period and the second period.
摘要翻译： 公开了一种用于产生具有作为参考时钟信号频率的分数或整数倍的频率的输出时钟信号的时钟分频器和方法。 在一个实施例中，时钟分频器在第一周期中将时钟信号除以第一因子，并在第二周期中除以第二除数，其中在第一周期之后的第二周期。 时钟分频器电路由时钟信号的第一个边沿触发并产生第一个信号。 同步电路耦合到时钟分频器以从第一信号产生第二信号，第二信号由时钟信号的第二边沿同步，其中第二边沿处于与第一边缘相反的方向。 选择器被耦合到同步电路和时钟分频器，以通过在第一周期和第二周期之间交替地选择第一信号和第二信号来产生输出信号。
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公开(公告)号：US06538475B1
公开(公告)日：2003-03-25
申请号：US09525459
申请日：2000-03-15
IPC分类号： H03D1300
CPC分类号： H03L7/089 , H03D13/004 , H04L7/033
摘要： A phase detector and corresponding method. The phase detector detects a transition of a first signal and generates an output signal having a first value if a transition of a second signal occurs before the transition of the first signal and having a second value if the transition of the second signal occurs after the transition of the first signal. The output signal is maintained at the generated value until another transition of the first signal is detected. A strobe signal may be used to strobe the output signal.
摘要翻译： 相位检测器及相应的方法。 相位检测器检测第一信号的转变，并且如果在第一信号的转变之前发生第二信号的转变并且如果在转换之后发生第二信号的转变而具有第二值，则产生具有第一值的输出信号 的第一个信号。 输出信号保持在产生的值，直到检测到第一信号的另一个转换。 选通信号可以用于选通输出信号。
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公开(公告)号：US06438178B1
公开(公告)日：2002-08-20
申请号：US09373080
申请日：1999-08-11
IPC分类号： H04L2506
CPC分类号： H04L25/06 , H04L25/03885 , H04L25/4912
摘要： An integrated circuit for receiving and recovering an incoming electrical signal of a digital data bit stream transmitted over a communication channel, and comprising an equaliser circuit adapted to reshape the electrical signal to be provided to, a CDR circuit adapted to receive the reshaped electrical signal and to recover data bit signal of the digital bit stream and to recover a clock signal encoded or embedded in the digital data stream.
摘要翻译： 一种用于接收和恢复通过通信信道发送的数字数据比特流的输入电信号的集成电路，并且包括适于重新形成要提供给适于接收重整电信号的CDR电路的电信号的均衡器电路， 以恢复数字位流的数据位信号，并恢复编码或嵌入在数字数据流中的时钟信号。
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公开(公告)号：US06973151B2
公开(公告)日：2005-12-06
申请号：US09893217
申请日：2001-06-26
申请人： Henning Lysdal , Eivind Johansen
发明人： Henning Lysdal , Eivind Johansen
CPC分类号： H04J3/0682 , H04J3/0685 , H04L7/0008 , H04L7/02
摘要： According one embodiment, an apparatus and method are disclosed for a dynamic phase aligning input interface. In the embodiment, a first device provides data to a second device. According to the embodiment, the interface is counter clocked, the second device being clocked by a first clock signal and providing a second clock signal source to the first device for clocking the data. The first device transmits the second clock signal and the data to the second device, with the second clock signal being delayed by the period of time required for the second clock signal source to propagate through the first device. The second device detects the phase of the first clock signal and the second clock signal and modifies the phase of the second clock signal source to align the phase of the first clock signal and the phase of the second clock signal.
摘要翻译： 根据一个实施例，公开了用于动态相位对准输入接口的装置和方法。 在该实施例中，第一设备向第二设备提供数据。 根据实施例，接口被计数器计时，第二设备由第一时钟信号计时，并将第二时钟信号源提供给第一设备以便计时数据。 第一设备将第二时钟信号和数据发送到第二设备，其中第二时钟信号被延迟第二时钟信号源通过第一设备传播所需的时间段。 第二装置检测第一时钟信号和第二时钟信号的相位，并且修改第二时钟信号源的相位以对准第一时钟信号的相位和第二时钟信号的相位。
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