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公开(公告)号：US6078515A
公开(公告)日：2000-06-20
申请号：US196624
申请日：1998-11-18
摘要： A memory system that includes a memory controller and memory modules that provide address and control signals to groups of memory components through multiple busses. In one embodiment, each memory module is coupled to an address/control buss. The use of multiple address/control busses provides the necessary bandwidth so as to allow for fast access and control of memory components. Memory components are grouped into banks of memory components with each bank including three memory components. Memory modules are configured with one, two, four, or more banks of memory components on a given memory module. In one embodiment, the memory system includes six 48-bit memory modules that use SDRAM memory components. The six memory modules are used in a set to form a 288-bit memory word. When 16 Mbit or 64 Mbit memory components are used, this configuration gives a range of memory configurations from 32 megabytes to 2 gigabytes.
摘要翻译： 一种存储器系统，其包括存储器控制器和通过多个总线向存储器组件组提供地址和控制信号的存储器模块。 在一个实施例中，每个存储器模块耦合到地址/控制总线。 使用多个地址/控制总线提供必要的带宽，以便允许快速访问和控制存储器组件。 存储器组件被分组成存储器组件的组，每个存储体包括三个存储器组件。 存储器模块在给定的存储器模块上配置有一个，两个，四个或更多组存储器组件。 在一个实施例中，存储器系统包括使用SDRAM存储器组件的六个48位存储器模块。 六个存储器模块用于一组以形成288位存储器字。 当使用16 Mbit或64 Mbit内存组件时，此配置可提供从32兆字节到2千兆字节的内存配置范围。
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公开(公告)号：US5870325A
公开(公告)日：1999-02-09
申请号：US60451
申请日：1998-04-14
摘要： A memory system that includes a memory controller and memory modules that provide address and control signals to groups of memory components through multiple busses. In one embodiment, each memory module is coupled to an address/control buss. The use of multiple address/control busses provides the necessary bandwidth so as to allow for fast access and control of memory components. Memory components are grouped into banks of memory components with each bank including three memory components. Memory modules are configured with one, two, four, or more banks of memory components on a given memory module. In one embodiment, the memory system includes six 48-bit memory modules that use SDRAM memory components. The six memory modules are used in a set to form a 288-bit memory word. When 16 Mbit or 64 Mbit memory components are used, this configuration gives a range of memory configurations from 32 megabytes to 2 gigabytes.
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3.发明授权
公开(公告)号：US6104417A
公开(公告)日：2000-08-15
申请号：US713779
申请日：1996-09-13
CPC分类号： G06T1/60 , G06F12/1081 , G06F12/1027 , G09G2360/125 , G09G5/39
摘要： A computer system provides dynamic memory allocation for graphics. The computer system includes a memory controller, a unified system memory, and memory clients each having access to the system memory via the memory controller. Memory clients can include a graphics rendering engine, a CPU, an image processor, a data compression/expansion device, an input/output device, a graphics back end device. The computer system provides read/write access to the unified system memory, through the memory controller, for each of the memory clients. Translation hardware is included for mapping virtual addresses of pixel buffers to physical memory locations in the unified system memory. Pixel buffers are dynamically allocated as tiles of physically contiguous memory. Translation hardware is implemented in each of the computational devices, which are included as memory clients in the computer system, including primarily the rendering engine.
摘要翻译： 计算机系统为图形提供动态内存分配。 计算机系统包括存储器控制器，统一系统存储器和存储器客户端，每个存储器客户端都可以通过存储器控制器访问系统存储器。 内存客户端可以包括图形呈现引擎，CPU，图像处理器，数据压缩/扩展设备，输入/输出设备，图形后端设备。 计算机系统通过存储器控制器为每个存储器客户端提供对统一系统存储器的读/写访问。 包括翻译硬件，用于将像素缓冲区的虚拟地址映射到统一系统内存中的物理内存位置。 像素缓冲区被动态分配为物理连续存储器的片。 在每个计算设备中实现翻译硬件，这些计算设备被包括作为计算机系统中的存储器客户机，主要包括呈现引擎。
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4.发明授权Direct memory access apparatus for transferring a block of data having discontinous addresses using an address calculating circuit 失效用于使用地址计算电路传送具有不连续地址的数据块的直接存储器存取装置
公开(公告)号：US06108722A
公开(公告)日：2000-08-22
申请号：US713602
申请日：1996-09-13
申请人： Mark W. Troeller , Michael L. Fuccio , Linda S. Gardner , Henry P. Moreton , Michael J. K. Nielsen
发明人： Mark W. Troeller , Michael L. Fuccio , Linda S. Gardner , Henry P. Moreton , Michael J. K. Nielsen
CPC分类号： G06F13/28
摘要： A method and arrangement for a dma transfer mode having multiple transactions is provided. The invention generates a set of transaction entries for a DMA transfer each of which contains information related to the address and command instruction of a transaction. The transaction entries are stored in an address/cmd-output-FIFO. The invention negotiates for the control of the system bus. Upon gaining control of the bus, the commands and address relate to each transaction are sequentially place on the system bus. If the transaction is a read operation, data received back from the system bus is first stored in a data-in-FIFO before being sent to the desired destination. If the transaction is a write operation, the data to be transferred is first stored in a data-out-FIFO before being timely place on the system bus for transferring to the desired destination. In either case, the number of data words transferred is monitored to determine when a transaction is complete. The number of transactions carried out is also monitored to determine when a DMA transfer is complete.
摘要翻译： 提供了具有多个事务的dma传送模式的方法和装置。 本发明生成一组用于DMA传输的事务条目，每个事务条目包含与事务的地址和命令指令相关的信息。 交易条目存储在地址/ cmd-output-FIFO中。 本发明协商用于控制系统总线。 在获得对总线的控制之后，与系统总线相关的命令和地址与每个事务相关。 如果事务是读取操作，则从系统总线接收的数据首先被存储在FIFO数据中，然后再发送到所需的目的地。 如果事务是写入操作，则要被传送的数据首先存储在数据输出FIFO中，然后及时放置在系统总线上以传送到所需目的地。 在这两种情况下，监视传输的数据字数，以确定交易何时完成。 还监控执行的事务数，以确定DMA传输何时完成。
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公开(公告)号：US4920486A
公开(公告)日：1990-04-24
申请号：US123382
申请日：1987-11-23
IPC分类号： G06F13/368 , G06F13/378
CPC分类号： G06F13/378
摘要： Each user of an intercommunicastion bus is associated with a distinct channel of an arbitration bus and maintains a priority record indicating its current priority status against each other user. During a contention interval each user then seeking to use the intercommunication bus bids for use of it by transmitting a bus request signal and makes an analysis of the signals to ascertain if it has a dominating priority for initiating a transaction on the bus, and access is granted accordingly. During the use-signal interval a user then using the intercommunication bus transmits an in-use signal used to up-date priority records with the effect of giving the last using user lowest priority. For transactions which require a response from a user other than the one initiating the transaction, a second round of bidding is conducted to determine whether any user is qualified to respond and if so which will be enabled to do so. When the response bidding shows no bidders the system immediately initiates bidding for a new transaction.
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6.发明授权
公开(公告)号：US5129089A
公开(公告)日：1992-07-07
申请号：US771784
申请日：1991-10-03
摘要： Interlocking of addresses in a system with parallel processors using a common memory space is managed by maintaining for each processor a record of the lock state of the system. When a processor seeks to initiate a transaction, the transaction is analyzed against the lock state record, and the processor's request for access to an intercommunication bus is transmitted only when the lock state of the system is in condition to process the transaction. By monitoring and analyzing bus transactions, the lock state record of each processor is maintained up to date. By thus blocking a transaction involving a locked address before the bus is requested, the tying up of the bus in futile activity is avoided.
摘要翻译： 通过为每个处理器维护系统的锁定状态的记录来管理具有使用公共存储器空间的并行处理器的系统中的地址的联锁。 当处理器试图启动事务时，针对锁定状态记录来分析事务，并且只有当系统的锁定状态处于事务处理条件时才传送处理器访问互通总线的请求。 通过监视和分析总线事务，每个处理器的锁状态记录保持最新。 因此，在要求总线之前，因此阻止涉及锁定地址的事务，避免了无效活动中的公共汽车的捆绑。
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7.发明授权
公开(公告)号：US5036493A
公开(公告)日：1991-07-30
申请号：US494672
申请日：1990-03-15
CPC分类号： G11C7/22 , G11C8/12 , G11C8/18 , H04N19/423 , H04N19/61
摘要： A computer memory system has multiple memory banks, only one of which can be accessed at any one instant in time. A memory bank decoder determines which of the memory banks is being accessed. The decoded bank enable signals generated by the decoder are used to send memory clocking signals only to the memory bank which is being accessed. In addition, each memory bank includes a clocked address signal buffer and a clocked data signal buffer. Clock signals are sent only to the address and data buffers in the memory bank which is being accessed. As a result, only the selected memory bank has its address and data buffers updated. All the other memory banks remain in a quiescent state, because no control signal, address signals, or data signals are sent to those memory banks. This eliminates the energy usage that would otherwise be associated with the idle memory banks, including both the energy used by the memory chips in the idle memory banks, as well as the energy associated with changing the state of the address and data lines connected to those memory chips.
摘要翻译： 计算机存储器系统具有多个存储器组，其中只有一个可以在任何一个时刻被访问。 存储体解码器确定正在访问哪些存储体。 由解码器产生的解码存储体使能信号仅用于将存储器时钟信号发送到正被存取的存储体。 此外，每个存储体包括时钟地址信号缓冲器和时钟数据信号缓冲器。 时钟信号仅发送到正被访问的存储体中的地址和数据缓冲器。 因此，只有选定的存储体才能更新其地址和数据缓冲区。 所有其他存储体保持静止状态，因为没有控制信号，地址信号或数据信号被发送到这些存储体。 这消除了否则将与空闲存储体相关联的能量使用，包括空闲存储体中的存储器芯片所使用的能量以及与改变连接到这些存储器的地址和数据线的状态相关联的能量 内存芯片
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8.发明授权Interrupt servicing and command acknowledgement system using distributed arbitration apparatus and shared bus 失效使用分布式仲裁设备和共享总线的中断服务和命令确认系统
公开(公告)号：US5038274A
公开(公告)日：1991-08-06
申请号：US437347
申请日：1989-11-15
IPC分类号： G06F13/378
CPC分类号： G06F13/378
摘要： Each user of an intercommunication bus is associated with a distinct channel of an arbitration bus and maintains a priority record indicating its current priority status against each other user. During a contention interval each user then seeking to use the intercommunication bus bids for use of it by transmitting a bus request signal and makes an analysis of the signals to ascertain if it has dominating priority for initiating a transaction on the bus, and access is granted accordingly. During the use-signal interval a user then using the intercommunication bus transmits an in-use signal used to up-date priority records with the effect of giving the last using user lowest priority. For transactions which require a response from a user other than the one initiating the transaction, a second round of bidding is conducted to determine whether any user is qualified to respond and if so which will be enabled to do so. When the response bidding shows no bidders the system immediately initiates bidding for a new transaction.
摘要翻译： 互通总线的每个用户与仲裁总线的不同信道相关联，并且保持指示其对彼此用户的当前优先级状态的优先级记录。 在争用间隔期间，每个用户然后寻求使用互通总线出价以通过发送总线请求信号并对信号进行分析，以确定其是否具有在总线上启动交易的主导优先级，并且允许访问 相应地。 在使用信号间隔期间，用户然后使用互通总线发送用于最新优先级记录的用途信号，具有给予最后使用用户最低优先级的效果。 对于需要除了启动交易的用户以外的用户作出回应的交易，进行第二轮投标以确定任何用户是否有资格回应，如果是这样，则可以启用此操作。 当响应投标显示没有投标人时，系统立即启动新交易的投标。
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