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    Technique for strain engineering in silicon-based transistors by using implantation techniques for forming a strain-inducing layer under the channel region
    6.
    发明授权
    Technique for strain engineering in silicon-based transistors by using implantation techniques for forming a strain-inducing layer under the channel region 有权
    通过使用用于在沟道区域下形成应变诱导层的注入技术在硅基晶体管中进行应变工程的技术

    公开(公告)号：US07871877B2

    公开(公告)日：2011-01-18

    申请号：US12015692

    申请日：2008-01-17

    申请人： Uwe Griebenow ,  Kai Frohberg ,  Martin Gerhardt

    发明人： Uwe Griebenow ,  Kai Frohberg ,  Martin Gerhardt

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054

    摘要： By incorporating a semiconductor species having the same valence and a different covalent radius compared to the base semiconductor material on the basis of an ion implantation process, a strain-inducing material may be positioned locally within a transistor at an appropriate manufacturing stage, thereby substantially not contributing to overall process complexity and also not affecting the further processing of the semiconductor device. Hence, a high degree of flexibility may be provided with respect to enhancing transistor performance in a highly local manner.

    摘要翻译： 通过在离子注入工艺的基础上结合具有与基底半导体材料相比具有相同价态和不同共价半径的半导体物质，应变诱导材料可以在适当的制造阶段局部地定位在晶体管内，从而基本上不 有助于整个过程的复杂性，也不影响半导体器件的进一步处理。 因此，可以以高度局部的方式提高晶体管性能方面的高度的灵活性。

    Double deposition of a stress-inducing layer in an interlayer dielectric with intermediate stress relaxation in a semiconductor device
    7.
    发明授权
    Double deposition of a stress-inducing layer in an interlayer dielectric with intermediate stress relaxation in a semiconductor device 有权
    在半导体器件中具有中等应力松弛的层间电介质中的应力诱导层双重沉积

    公开(公告)号：US08349744B2

    公开(公告)日：2013-01-08

    申请号：US12272273

    申请日：2008-11-17

    申请人： Kai Frohberg ,  Uwe Griebenow ,  Katrin Reiche ,  Heike Berthold

    发明人： Kai Frohberg ,  Uwe Griebenow ,  Katrin Reiche ,  Heike Berthold

    IPC分类号： H01L21/31

    CPC分类号： H01L21/823807 ,  H01L29/7843

    摘要： Enhanced efficiency of a stress relaxation implantation process may be achieved by depositing a first layer of reduced thickness and relaxing the same at certain device regions, thereby obtaining an enhanced amount of substantially relaxed dielectric material in close proximity to the transistor under consideration, wherein a desired high amount of stressed dielectric material may be obtained above other transistors by performing a further deposition process. Hence, the negative effect of the highly stressed dielectric material for specific transistors, for instance in densely packed device regions, may be significantly reduced by depositing the highly stressed dielectric material in two steps with an intermediate relaxation implantation process.

    摘要翻译： 应力松弛注入工艺的增强的效率可以通过沉积厚度较小的第一层并在某些器件区域放松应力松弛注入工艺，从而获得在考虑的晶体管附近获得增加量的基本上松弛的电介质材料，其中期望的 通过进行另外的沉积工艺，可以在其它晶体管之上获得大量的应力介电材料。 因此，通过用中间松弛注入工艺在两个步骤中沉积高应力电介质材料，可以显着地降低高应力电介质材料对特定晶体管（例如密集封装器件区域）的负面影响。

    Reduced silicon thickness of N-channel transistors in SOI CMOS devices
    8.
    发明授权
    Reduced silicon thickness of N-channel transistors in SOI CMOS devices 有权
    降低SOI CMOS器件中N沟道晶体管的硅厚度

    公开(公告)号：US08324039B2

    公开(公告)日：2012-12-04

    申请号：US12776742

    申请日：2010-05-10

    申请人： Uwe Griebenow

    发明人： Uwe Griebenow

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/84 ,  H01L27/1203

    摘要： In sophisticated SOI devices, the thickness of the active semiconductor layer in the N-channel transistor may be reduced compared to the P-channel transistor for a given transistor configuration, thereby obtaining a significant increase in performance of the N-channel transistor without negatively affecting performance of the P-channel transistor.

    摘要翻译： 在复杂的SOI器件中，与用于给定晶体管配置的P沟道晶体管相比，N沟道晶体管中的有源半导体层的厚度可能会降低，从而获得N沟道晶体管的性能显着提高而不会不利地影响 P沟道晶体管的性能。