Memory cell with nanocrystals or nanodots
    1.
    发明授权
    Memory cell with nanocrystals or nanodots 有权
    具有纳米晶体或纳米点的记忆体

    公开(公告)号:US07119395B2

    公开(公告)日:2006-10-10

    申请号:US10916013

    申请日:2004-08-11

    IPC分类号: H01L29/788

    摘要: The storage layer (6) is in each case present above a region in which the channel region (3) adjoins a source/drain region (2) and is in each case interrupted above an intervening middle part of the channel region (3). The storage layer (6) is formed by material of the gate dielectric (4) and contains silicon or germanium nanocrystals or nanodots introduced through ion implantation. The gate electrode (5) is widened at the flanks by electrically conductive spacers (7).

    摘要翻译: 存储层(6)在每种情况下都存在于沟道区域(3)邻接源极/漏极区域(2)的区域上方,并且在每个情况下都被中断在沟道区域(3)的中间部分之上。 存储层(6)由栅极电介质(4)的材料形成,并且包含通过离子注入引入的硅或锗纳米晶体或纳米点。 栅电极(5)通过导电间隔物(7)在侧面加宽。

    Programmable structure, a memory, a display and a method for reading data from a memory cell
    3.
    发明申请
    Programmable structure, a memory, a display and a method for reading data from a memory cell 审中-公开
    可编程结构,存储器,显示器和用于从存储器单元读取数据的方法

    公开(公告)号:US20070195611A1

    公开(公告)日:2007-08-23

    申请号:US11360149

    申请日:2006-02-23

    IPC分类号: G11C7/10

    摘要: The invention refers to an improved programmable structure, an improved memory, an improved display and an improved method for reading data from a memory cell. More particularly, embodiments of the invention provide a programmable structure and a memory, whereby a programmed state of the programmable structure and a programmed state of a memory cell of the memory can be read out with a simple method. According a further aspect of the present invention, the stored data of the programmable structure and the stored data of the memory device can be read out according an improved method. In accordance with one exemplary embodiment of the present invention, a programmable structure comprises an ion conductor layer, a modifying device coupled to the ion conductor layer, the modifying device being operable to change an electromagnetic property of the ion conductor layer, an emitting device for sending an electromagnetic radiation to the ion conductor layer and a receiving device for receiving an electromagnetic radiation from the ion conductor layer. The ion conductor layer is configured that when a bias is applied across the ion conductor layer an electromagnetic property of the ion conductor layer is changed. Therefore it is possible to program different states referring to different electromagnetic properties of the ion conductor layers. The different states of the ion conductor layer can be read by sending an electromagnetic radiation to the ion conductor layer and receiving the electromagnetic radiation from the ion conductor layer.

    摘要翻译: 本发明涉及改进的可编程结构,改进的存储器,改进的显示器和用于从存储器单元读取数据的改进方法。 更具体地,本发明的实施例提供可编程结构和存储器,由此可以用简单的方法读出可编程结构的编程状态和存储器的存储单元的编程状态。 根据本发明的另一方面,可以根据改进的方法读出可编程结构的存储数据和存储器件的存储数据。 根据本发明的一个示例性实施例,可编程结构包括离子导体层,耦合到离子导体层的修改设备,修改设备可操作以改变离子导体层的电磁特性,用于 向离子导体层发送电磁辐射和从离子导体层接收电磁辐射的接收装置。 离子导体层被配置为当跨越离子导体层施加偏压时,离子导体层的电磁特性改变。 因此,可以根据离子导体层的不同电磁特性编程不同的状态。 可以通过向离子导体层发送电磁辐射并接收来自离子导体层的电磁辐射来读取离子导体层的不同状态。

    Method for fabricating a semiconductor memory cell
    4.
    发明授权
    Method for fabricating a semiconductor memory cell 失效
    半导体存储单元的制造方法

    公开(公告)号:US07214587B2

    公开(公告)日:2007-05-08

    申请号:US11074946

    申请日:2005-03-09

    IPC分类号: H01L21/336

    摘要: Semiconductor memory cell and also a corresponding fabrication method are described, in which a first or bottom electrode device of the memory element of the semiconductor memory cell according to the invention and the gate electrode device of the underlying field effect transistor as selection transistor of the semiconductor memory cell are formed as the same material region or with a common material region.

    摘要翻译: 描述了半导体存储单元以及相应的制造方法,其中根据本发明的半导体存储单元的存储元件的第一或下部电极器件和作为半导体的选择晶体管的底层场效应晶体管的栅极电极器件 存储单元形成为相同的材料区域或与公共材料区域形成。

    Intergrated semiconductor memory and method for producing an integrated semiconductor memory
    5.
    发明申请
    Intergrated semiconductor memory and method for producing an integrated semiconductor memory 有权
    集成半导体存储器和集成半导体存储器的制造方法

    公开(公告)号:US20060291268A1

    公开(公告)日:2006-12-28

    申请号:US11441805

    申请日:2006-05-26

    IPC分类号: G11C17/00

    摘要: An integrated semiconductor memory includes a storage medium (6) arranged between two electrodes (10, 20), which storage medium may be a phase change medium, for example. The storage medium (6) can be put into a first state or a second state by means of an electric current, as a result of which an item of information can be stored. According to embodiments of the invention, a layer plane (L) is provided in which impurity particles made from a material (4) are embedded, as a result of which the current density in the storage medium is locally increased and the programming current required for reprogramming is reduced. As a result, the current consumption of memory elements containing a phase change medium is reduced, so that for the first time they can be embodied with minimal feature size, together with other components such as transistors, and integrated into a single semiconductor circuit and no longer have to be arranged in separate subcircuits.

    摘要翻译: 集成半导体存储器包括布置在两个电极(10,20)之间的存储介质(6),该存储介质可以是例如相变介质。 存储介质(6)可以通过电流进入第一状态或第二状态,结果可以存储信息项。 根据本发明的实施例,提供了一种层状平面(L),其中嵌入由材料(4)制成的杂质颗粒,结果存储介质中的电流密度局部增加,并且需要编程电流 重编程减少。 结果,包含相变介质的存储元件的电流消耗减少,使得它们可以首次以最小的特征尺寸与其他元件(例如晶体管)一体化,并且集成到单个半导体电路中,并且不存在 更长的时间必须在单独的子电路中排列。

    Method for fabricating a semiconductor memory cell
    6.
    发明申请
    Method for fabricating a semiconductor memory cell 失效
    半导体存储单元的制造方法

    公开(公告)号:US20050201143A1

    公开(公告)日:2005-09-15

    申请号:US11074946

    申请日:2005-03-09

    摘要: Semiconductor memory cell and also a corresponding fabrication method are described, in which a first or bottom electrode device of the memory element of the semiconductor memory cell according to the invention and the gate electrode device of the underlying field effect transistor as selection transistor of the semiconductor memory cell are formed as the same material region or with a common material region.

    摘要翻译: 描述了半导体存储单元以及相应的制造方法,其中根据本发明的半导体存储单元的存储元件的第一或下部电极器件和作为半导体的选择晶体管的底层场效应晶体管的栅极电极器件 存储单元形成为相同的材料区域或与公共材料区域形成。

    Integrated circuit having a resistive memory
    7.
    发明授权
    Integrated circuit having a resistive memory 有权
    具有电阻存储器的集成电路

    公开(公告)号:US07787279B2

    公开(公告)日:2010-08-31

    申请号:US11441805

    申请日:2006-05-26

    IPC分类号: G11C11/00

    摘要: An integrated semiconductor memory includes a storage medium (6) arranged between two electrodes (10, 20), which storage medium may be a phase change medium, for example. The storage medium (6) can be put into a first state or a second state by means of an electric current, as a result of which an item of information can be stored. According to embodiments of the invention, a layer plane (L) is provided in which impurity particles made from a material (4) are embedded, as a result of which the current density in the storage medium is locally increased and the programming current required for reprogramming is reduced. As a result, the current consumption of memory elements containing a phase change medium is reduced, so that for the first time they can be embodied with minimal feature size, together with other components such as transistors, and integrated into a single semiconductor circuit and no longer have to be arranged in separate subcircuits.

    摘要翻译: 集成半导体存储器包括布置在两个电极(10,20)之间的存储介质(6),该存储介质可以是例如相变介质。 存储介质(6)可以通过电流进入第一状态或第二状态,结果可以存储信息项。 根据本发明的实施例,提供了一种层状平面(L),其中嵌入由材料(4)制成的杂质颗粒,结果存储介质中的电流密度局部增加,并且需要编程电流 重编程减少。 结果,包含相变介质的存储元件的电流消耗减少,使得它们可以首次以最小的特征尺寸与其他元件(例如晶体管)一体化,并且集成到单个半导体电路中,并且不存在 更长的时间必须在单独的子电路中排列。

    Fabricating memory components (PCRAMS) including memory cells based on a layer that changes phase state
    8.
    发明授权
    Fabricating memory components (PCRAMS) including memory cells based on a layer that changes phase state 有权
    基于改变阶段状态的层,构建存储器组件(PCRAMS),包括存储器单元

    公开(公告)号:US07329561B2

    公开(公告)日:2008-02-12

    申请号:US11210112

    申请日:2005-08-24

    IPC分类号: H01L21/06

    摘要: A method is describe for fabricating memory components including memory cells based on an active material of an active layer, the phase state of which can be changed and which is enclosed between a bottom electrode and a top electrode. To reduce the current intensity of the programming current and the erase current required for programming and erasing of the memory element and therefore the quantity of heat which is required to change the phase state, a nanoporous aluminium oxide layer is used as a mask during the production of the active layer or the interface with the electrodes. The nanoporous aluminium oxide layer can be used as a positive mask, as a negative mask, or used directly as an insulating current aperture. The contact surface between electrode and active layer can be set in virtually any desired form by varying the process parameters of the aluminium oxide mask. Since the typical cell area of the memory cell is significantly larger than the mean diameter of the nanopores, a good homogeneity and reproducibility of the contacts results from a production engineering standpoint.

    摘要翻译: 描述了一种用于制造包括基于有源层的活性材料的存储器单元的存储器组件的方法,该有源层的相位状态可以被改变并且被包围在底部电极和顶部电极之间。 为了降低编程电流的电流强度和存储元件的编程和擦除所需的擦除电流以及因此改变相位状态所需的热量,在生产过程中使用纳米孔氧化铝层作为掩模 的活性层或与电极的界面。 纳米多孔氧化铝层可以用作正掩模,作为负掩模,或直接用作绝缘电流孔。 通过改变氧化铝掩模的工艺参数,电极和有源层之间的接触表面可以几乎任意形成。 由于存储单元的典型单元面积显着大于纳米孔的平均直径,所以从生产工程的观点来看,接触的良好的均匀性和再现性。

    Method and device for driving solid electrolyte cells
    9.
    发明申请
    Method and device for driving solid electrolyte cells 审中-公开
    用于驱动固体电解质电池的方法和装置

    公开(公告)号:US20060203430A1

    公开(公告)日:2006-09-14

    申请号:US11343923

    申请日:2006-01-31

    IPC分类号: H01G9/04

    摘要: An electrical switching device comprises a switching element and a heating device for heating the switching element. The switching element comprises a first electrode, a second electrode, and an electrolyte layer arranged between and contact-connected to the first and second electrode. The switching element is configured to establish a conducting path between the first and second electrodes via the electrolyte layer by conduction elements having diffused from the first electrode into the electrolyte layer.

    摘要翻译: 电气开关装置包括开关元件和用于加热开关元件的加热装置。 开关元件包括第一电极,第二电极和布置在第一和第二电极之间并与之接触的电解质层。 开关元件被配置为通过从第一电极扩散到电解质层的导电元件经由电解质层在第一和第二电极之间建立导电路径。

    Fabricating memory components (PCRAMS) including memory cells based on a layer that changes phase state
    10.
    发明申请
    Fabricating memory components (PCRAMS) including memory cells based on a layer that changes phase state 有权
    基于改变阶段状态的层,构建存储器组件(PCRAMS),包括存储器单元

    公开(公告)号:US20060046379A1

    公开(公告)日:2006-03-02

    申请号:US11210112

    申请日:2005-08-24

    IPC分类号: H01L21/8244

    摘要: A method is describe for fabricating memory components including memory cells based on an active material of an active layer, the phase state of which can be changed and which is enclosed between a bottom electrode and a top electrode. To reduce the current intensity of the programming current and the erase current required for programming and erasing of the memory element and therefore the quantity of heat which is required to change the phase state, a nanoporous aluminium oxide layer is used as a mask during the production of the active layer or the interface with the electrodes. The nanoporous aluminium oxide layer can be used as a positive mask, as a negative mask, or used directly as an insulating current aperture. The contact surface between electrode and active layer can be set in virtually any desired form by varying the process parameters of the aluminium oxide mask. Since the typical cell area of the memory cell is significantly larger than the mean diameter of the nanopores, a good homogeneity and reproducibility of the contacts results from a production engineering standpoint.

    摘要翻译: 描述了一种用于制造包括基于有源层的活性材料的存储器单元的存储器组件的方法,该有源层的相位状态可以被改变并且被包围在底部电极和顶部电极之间。 为了降低编程电流的电流强度和存储元件的编程和擦除所需的擦除电流以及因此改变相位状态所需的热量,在生产过程中使用纳米孔氧化铝层作为掩模 的活性层或与电极的界面。 纳米多孔氧化铝层可以用作正掩模,作为负掩模,或直接用作绝缘电流孔。 通过改变氧化铝掩模的工艺参数,电极和有源层之间的接触表面可以几乎任意形成。 由于存储单元的典型单元面积显着大于纳米孔的平均直径,所以从生产工程的观点来看,接触的良好的均匀性和再现性。