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    Buffered audio system with synchronizing bus controller
    2.
    发明授权
    Buffered audio system with synchronizing bus controller 有权
    缓冲音频系统与同步总线控制器

    公开(公告)号：US08824956B1

    公开(公告)日：2014-09-02

    申请号：US13675723

    申请日：2012-11-13

    Applicant: Marvell International Ltd.

    Inventor： Zhenyu Zhang ,  Sheng Lu ,  Jing Jiang ,  Victor Lin ,  Hunghsin Kuo

    IPC: H04H40/00 ,  G06F13/42

    CPC classification number: G06F13/42 ,  G06F13/4291 ,  H04W4/00

    Abstract: A method includes receiving samples of audio data and storing the samples of audio data in a buffer. Each of the samples of audio data includes a plurality of bits. The method also includes transmitting each of the plurality of bits, of each of the samples of audio data retrieved from the buffer, across a single-bit bus; and subsequent to transmitting each of the samples, transmitting a selected number of dummy bits across the single-bit bus. The selected number is greater than one. The method further includes analyzing activity of the buffer and, based on the activity of the buffer, dynamically adjusting the selected number. The method also includes acquiring the samples of audio data transmitted across the single-bit bus and ignoring the dummy bits. The method further includes generating analog signals in response to the samples of audio data acquired across the single-bit bus.

    Abstract translation: 一种方法包括接收音频数据的样本并将音频数据的样本存储在缓冲器中。 音频数据的每个样本包括多个比特。 该方法还包括通过单位总线传送从缓冲器检索的每个音频数据样本的多个比特中的每一个; 并且在发送每个采样之后，在单位总线上发送选定数量的虚拟位。 所选号码大于1。 该方法还包括分析缓冲器的活动，并且基于缓冲器的活动来动态地调整所选择的数量。 该方法还包括获取通过单位总线发送的音频数据的样本，并忽略虚拟位。 该方法还包括响应于跨单位总线获取的音频数据的样本产生模拟信号。

    Self governing power management architecture that allows independent management of devices based on clock signals and a plurality of control signals written to control registers
    3.
    发明授权
    Self governing power management architecture that allows independent management of devices based on clock signals and a plurality of control signals written to control registers 有权
    自调节电源管理架构，允许基于时钟信号和写入控制寄存器的多个控制信号独立管理设备

    公开(公告)号：US08826047B1

    公开(公告)日：2014-09-02

    申请号：US13895775

    申请日：2013-05-16

    Applicant: Marvell International Ltd.

    Inventor： Jun Zhu ,  Ian Swarbrick ,  Joseph Jun Cao ,  Sheng Lu ,  Pantas Sutardja

    IPC: G06F1/32

    CPC classification number: G06F1/3206 ,  G06F1/3209 ,  G06F1/3237 ,  G06F1/3287 ,  Y02D10/128 ,  Y02D10/171

    Abstract: A first power management module includes a power management interface to communicate with a power management bus and manages power states of a first device communicating with a system bus. The power management interface includes a first interface to communicate a first control signal to transition the first device from a first power state to a second power state, a second interface to communicate a second control signal to turn on or off a power supply to the first device, and a third interface to communicate a third control signal to turn on or off a clock of the first device. A second power management module manages power consumption of the first device, independently of a second device communicating with the system bus, based on the power states of the first device using one or more of the first control signal, the second control signal, and the third control signal.

    Abstract translation: 第一电源管理模块包括电源管理接口，用于与电源管理总线通信并管理与系统总线通信的第一设备的电源状态。 电源管理接口包括用于传送第一控制信号以将第一设备从第一电源状态转换到第二电源状态的第一接口，用于传送第二控制信号以打开或关闭到第一电源的电源的第二接口 设备和第三接口，用于传送第三控制信号以打开或关闭第一设备的时钟。 第二电源管理模块基于使用第一控制信号，第二控制信号和第二控制信号中的一个或多个的第一设备的功率状态，独立于与系统总线通信的第二设备来管理第一设备的功耗 第三控制信号。

    Providing error correcting code (ECC) capability for memory
    4.
    发明授权
    Providing error correcting code (ECC) capability for memory 有权

    公开(公告)号：US10198310B1

    公开(公告)日：2019-02-05

    申请号：US14940023

    申请日：2015-11-12

    Applicant: Marvell International Ltd.

    Inventor： Jun Zhu ,  Joseph Jun Cao ,  Sheng Lu ,  Pantas Sutardja

    IPC: G11C29/00 ,  G06F11/10 ,  G06F11/00 ,  G11C16/34 ,  H03M13/13 ,  H03M13/00

    Abstract: A method includes, in at least one aspect, designating a first region of a memory device for storing data of a first type and first error correcting code (ECC) data; designating a second region for storing data of a second type and second ECC data; receiving the data of the first type; generating the first ECC data for the data of the first type using a first ECC associated with a first ECC protection level; storing the data of the first type and the first ECC data in adjacent locations of the first region; receiving the data of the second type; generating the second ECC data for the data of the second type using a second ECC associated with a second ECC protection level; and storing the data of the second type and the second ECC data in the second region.

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