公开(公告)号：US06403462B1

公开(公告)日：2002-06-11

申请号：US09321848

申请日：1999-05-28

申请人： Masahiko Hasunuma ,  Hisashi Kaneko ,  Shohei Shima ,  Sachiyo Ito

发明人： Masahiko Hasunuma ,  Hisashi Kaneko ,  Shohei Shima ,  Sachiyo Ito

IPC分类号： H01L214763

CPC分类号： H01L21/76847 ,  H01L21/32051 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device manufacturing method of the this invention having the step of forming an interlayer insulating film on a semiconductor substrate, the step of making interconnection groove in the interlayer insulating film, the step of filling the inside of the interconnection groove with a conductive film which is made of a first substance and is thicker than the depth of the interconnection groove, the step of thermally stabilizing the size of crystal grains in an Al film either at the same time or after the Al film has been formed, the step of forming a Cu film on the Al film, the step of selectively forming &thgr; phase layers in a crystal grain boundary of the Al film by causing Cu to selectively diffuse into the crystal grain boundary of Al film and of allowing the &thgr; phase layers to divide the Al film in the interconnection groove into fine Al interconnections shorter than the Blech critical length, and the step of removing the Al film and Cu film outside the interconnection groove.

摘要翻译： 本发明的半导体器件制造方法具有在半导体衬底上形成层间绝缘膜的步骤，在层间绝缘膜中形成互连槽的步骤，用导电膜填充互连槽的内部的步骤 由第一物质制成并且比互连槽的深度厚，在Al膜同时或在Al膜形成之后热稳定晶粒尺寸的步骤，形成 Al膜上的Cu膜，通过使Cu选择性地扩散到Al膜的晶粒边界并允许θ相层分割Al膜，在Al膜的晶粒边界中选择性地形成θ相层的步骤 在互连槽中成为比Blech临界长度短的精细Al互连，以及除去Interconnec外部的Al膜和Cu膜的步骤 沟槽。

公开(公告)号：US06552434B2

公开(公告)日：2003-04-22

申请号：US10062468

申请日：2002-02-05

申请人： Masahiko Hasunuma ,  Hisashi Kaneko ,  Shohei Shima ,  Sachiyo Ito

发明人： Masahiko Hasunuma ,  Hisashi Kaneko ,  Shohei Shima ,  Sachiyo Ito

IPC分类号： H01L2348

CPC分类号： H01L21/76847 ,  H01L21/32051 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device manufacturing method of the this invention having the step of forming an interlayer insulating film on a semiconductor substrate, the step of making interconnection groove in the interlayer insulating film, the step of filling the inside of the interconnection groove with a conductive film which is made of a first substance and is thicker than the depth of the interconnection groove, the step of thermally stabilizing the size of crystal grains in an Al film either at the same time or after the Al film has been formed, the step of forming a Cu film on the Al film, the step of selectively forming &thgr; phase layers in a crystal grain boundary of the Al film by causing Cu to selectively diffuse into the crystal grain boundary of Al film and of allowing the &thgr; phase layers to divide the Al film in the interconnection groove into fine Al interconnections shorter than the Blech critical length, and the step of removing the Al film and Cu film outside the interconnection groove.

公开(公告)号：US07921401B2

公开(公告)日：2011-04-05

申请号：US11703218

申请日：2007-02-07

申请人： Sachiyo Ito ,  Masahiko Hasunuma ,  Hisashi Kaneko

发明人： Sachiyo Ito ,  Masahiko Hasunuma ,  Hisashi Kaneko

IPC分类号： G06F17/50 ,  G06F11/22

CPC分类号： G06F17/5018 ,  G06F17/5068 ,  G06F2217/80 ,  H01L2924/0002 ,  H01L2924/00

摘要： A stress analysis method is provided: including dividing, by using a division unit, an inside of a chip into a plurality of analysis areas, deriving, by using a composite property derivation unit, a composite property into which physical property values of a plurality of materials included in an analysis area are compounded, about each of the plurality of analysis areas on the basis of wiring structure data for each of the plurality of analysis areas, and creating, by using a stress analysis unit, a three-dimensional model of a finite element method which uses each analysis area as an element, to apply the composite property to each element, and to perform a stress analysis.

摘要翻译： 提供一种应力分析方法，包括：通过使用分割单元将芯片的内部划分为多个分析区域，通过使用复合特性导出单元导出多个分析区域的物理属性值的复合特性 基于多个分析区域中的每一个的布线结构数据，分析包括在分析区域中的材料，并且基于多个分析区域中的每一个，分别对每个分析区域进行复合，并且通过使用应力分析单元来创建三维模型 使用每个分析区域作为元素的有限元法，将复合属性应用于每个元素，并进行应力分析。

公开(公告)号：US20070204243A1

公开(公告)日：2007-08-30

申请号：US11703218

申请日：2007-02-07

申请人： Sachiyo Ito ,  Masahiko Hasunuma ,  Hisashi Kaneko

发明人： Sachiyo Ito ,  Masahiko Hasunuma ,  Hisashi Kaneko

IPC分类号： G06F17/50 ,  G06F17/10 ,  G06F19/00 ,  G01L19/00

CPC分类号： G06F17/5018 ,  G06F17/5068 ,  G06F2217/80 ,  H01L2924/0002 ,  H01L2924/00

摘要： A stress analysis method is provided: including dividing, by using a division unit, an inside of a chip into a plurality of analysis areas, deriving, by using a composite property derivation unit, a composite property into which physical property values of a plurality of materials included in an analysis area are compounded, about each of the plurality of analysis areas on the basis of wiring structure data for each of the plurality of analysis areas, and creating, by using a stress analysis unit, a three-dimensional model of a finite element method which uses each analysis area as an element, to apply the composite property to each element, and to perform a stress analysis.

摘要翻译： 提供一种应力分析方法，包括：通过使用分割单元将芯片的内部划分为多个分析区域，通过使用复合特性导出单元导出多个分析区域的物理属性值的复合特性 基于多个分析区域中的每一个的布线结构数据，分析包括在分析区域中的材料，并且基于多个分析区域中的每一个，分别对每个分析区域进行复合，并且通过使用应力分析单元来创建三维模型 使用每个分析区域作为元素的有限元法，将复合属性应用于每个元素，并进行应力分析。

公开(公告)号：US20060068600A1

公开(公告)日：2006-03-30

申请号：US11181908

申请日：2005-07-15

申请人： Hiroshi Toyoda ,  Sachiyo Ito ,  Masahiko Hasunuma ,  Hisashi Kaneko

发明人： Hiroshi Toyoda ,  Sachiyo Ito ,  Masahiko Hasunuma ,  Hisashi Kaneko

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76838 ,  C23C14/0635 ,  C23C14/165

摘要： A method of manufacturing a semiconductor device according to an aspect of the present invention comprises forming a plated film on a substrate which has a recessed portion on its surface so as to bury in the recessed portion by a plating method; forming over the plated film a compressive stress-applying film which is composed of a material having a thermal expansion coefficient of 60% or less compared with a thermal expansion coefficient of a metal composing the plated film; heat-treating while applying a compressive stress to the plated film by the compressive stress-applying film; and removing the compressive stress-applying film and the plated film which is not buried in the recessed portion.

摘要翻译： 根据本发明的一个方面的制造半导体器件的方法包括在其表面上具有凹陷部分的基板上形成镀膜，以便通过电镀方式将凹陷部分埋入其中; 在电镀膜上形成压缩应力施加膜，该压应力膜由与构成镀膜的金属的热膨胀系数相比具有60％以下的热膨胀系数的材料构成; 通过压应力施加膜向镀膜施加压应力时的热处理; 并且除去未埋设在凹部中的压应力施加膜和镀膜。

公开(公告)号：US06001461A

公开(公告)日：1999-12-14

申请号：US771388

申请日：1996-12-19

申请人： Hiroshi Toyoda ,  Hisashi Kaneko ,  Masahiko Hasunuma ,  Takashi Kawanoue ,  Hiroshi Tomita ,  Akihiro Kajita ,  Masami Miyauchi ,  Takashi Kawakubo ,  Sachiyo Ito

发明人： Hiroshi Toyoda ,  Hisashi Kaneko ,  Masahiko Hasunuma ,  Takashi Kawanoue ,  Hiroshi Tomita ,  Akihiro Kajita ,  Masami Miyauchi ,  Takashi Kawakubo ,  Sachiyo Ito

IPC分类号： H01L21/3205 ,  H01L23/528 ,  H01L23/532 ,  B32B9/00

CPC分类号： H01L23/532 ,  H01L21/32051 ,  H01L23/5283 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10T428/2457 ,  Y10T428/24926

摘要： An electronic part comprising an amorphous thin film formed on a substrate; and a metal wiring formed on the surface of the amorphous thin film; wherein an interatomic distance corresponding to a peak of halo pattern appearing in diffraction measurement of the amorphous thin film approximately matches with a spacing of a particular crystal plane defined with the first nearest interatomic distance of the metal wiring. An electronic part provided with a metal wiring formed of highly orientated crystal wherein half or more of all grain boundaries are small angle grain boundaries defined by one of grain boundaries with a relative misorientation of 10.degree. or less in tilt, rotation and combination thereof around orientation axes of neighboring crystal grains; coincidence boundaries where a .SIGMA. value is 10 or less; and grain boundaries with a relative misorientation of 3.degree. or less from the coincidence boundary. A method for manufacturing an electronic part, comprising the step of depositing a conductor layer which is mainly formed of one selected from Al and Cu on a substrate via an insulative layer, a barrier layer, a contact layer or an amorphous thin film layer wherein one element selected from Ga, In, Cd, Bi, Pb, Sn and Tl is supplied before or during the deposition of the conductor layer.

摘要翻译： 一种电子部件，包括形成在基板上的非晶薄膜; 以及形成在所述非晶薄膜的表面上的金属布线; 其中对应于在非晶薄膜的衍射测量中出现的晕轮图案的峰值的原子间距离大致与由金属布线的第一最接近的原子间距离限定的特定晶面的间隔相匹配。 一种电子部件，其具有由高取向晶体形成的金属布线，其中所有晶界的一半以上是由倾斜，旋转及其组合在取向方向上的相位差取向为10°以下的晶界之一限定的小角度晶界 相邻晶粒的轴; SIGMA值为10以下的重合边界; 晶界与重合边界的相对误差为3°以下。 一种电子部件的制造方法，其特征在于，包括以下步骤：通过绝缘层，阻挡层，接触层或无定形薄膜层，在基板上沉积主要由选自Al和Cu的一个导体层形成的步骤，其中一个 选自Ga，In，Cd，Bi，Pb，Sn和Tl的元素在导体层的沉积之前或期间提供。

公开(公告)号：US5709958A

公开(公告)日：1998-01-20

申请号：US451528

申请日：1995-05-26

申请人： Hiroshi Toyoda ,  Hisashi Kaneko ,  Masahiko Hasunuma ,  Takashi Kawanoue ,  Hiroshi Tomita ,  Akihiro Kajita ,  Masami Miyauchi ,  Takashi Kawakubo ,  Sachiyo Ito

发明人： Hiroshi Toyoda ,  Hisashi Kaneko ,  Masahiko Hasunuma ,  Takashi Kawanoue ,  Hiroshi Tomita ,  Akihiro Kajita ,  Masami Miyauchi ,  Takashi Kawakubo ,  Sachiyo Ito

IPC分类号： H01L21/3205 ,  H01L23/528 ,  H01L23/532 ,  H01L29/43

CPC分类号： H01L21/32051 ,  H01L23/5283 ,  H01L23/532 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10T428/12528 ,  Y10T428/12674 ,  Y10T428/12681

摘要： An electronic part comprising an amorphous thin film formed on a substrate; and a metal wiring formed on the surface of the amorphous thin film; wherein an interatomic distance corresponding to a peak of halo pattern appearing in diffraction measurement of the amorphous thin film approximately matches with a spacing of a particular crystal plane defined with the first nearest interatomic distance of the metal wiring. An electronic part provided with a metal wiring formed of highly orientated crystal wherein half or more of all grain boundaries are small angle grain boundaries defined by one of grain boundaries with a relative misorientation of 10.degree. or less in tilt, rotation and combination thereof around orientation axes of neighboring crystal grains; coincidence boundaries where a .SIGMA. value is 10 or less; and grain boundaries with a relative misorientation of 3.degree. or less from the coincidence boundary. A method for manufacturing an electronic part, comprising the step of depositing a conductor layer which is mainly formed of one selected from Al and Cu on a substrate via an insulative layer, a barrier layer, a contact layer or an amorphous thin film layer wherein one element selected from Ga, In, Cd, Bi, Pb, Sn and Tl is supplied before or during the deposition of the conductor layer.

摘要翻译： 一种电子部件，包括形成在基板上的非晶薄膜; 以及形成在所述非晶薄膜的表面上的金属布线; 其中对应于在非晶薄膜的衍射测量中出现的晕轮图案的峰值的原子间距离大致与由金属布线的第一最接近的原子间距离限定的特定晶面的间隔相匹配。 一种电子部件，其具有由高取向晶体形成的金属布线，其中所有晶界的一半以上是由倾斜，旋转及其组合在取向方向上的相位差取向为10°以下的晶界之一限定的小角度晶界 相邻晶粒的轴; SIGMA值为10以下的重合边界; 晶界与重合边界的相对误差为3°以下。 一种电子部件的制造方法，其特征在于，包括以下步骤：通过绝缘层，阻挡层，接触层或无定形薄膜层，在基板上沉积主要由选自Al和Cu的一个导体层形成的步骤，其中一个 选自Ga，In，Cd，Bi，Pb，Sn和Tl的元素在导体层的沉积之前或期间提供。

公开(公告)号：US07314827B2

公开(公告)日：2008-01-01

申请号：US11181908

申请日：2005-07-15

申请人： Hiroshi Toyoda ,  Sachiyo Ito ,  Masahiko Hasunuma ,  Hisashi Kaneko

发明人： Hiroshi Toyoda ,  Sachiyo Ito ,  Masahiko Hasunuma ,  Hisashi Kaneko

IPC分类号： H01L21/4763

CPC分类号： H01L21/76838 ,  C23C14/0635 ,  C23C14/165

摘要： A method of manufacturing a semiconductor device according to an aspect of the present invention comprises forming a plated film on a substrate which has a recessed portion on its surface so as to bury in the recessed portion by a plating method; forming over the plated film a compressive stress-applying film which is composed of a material having a thermal expansion coefficient of 60% or less compared with a thermal expansion coefficient of a metal composing the plated film; heat-treating while applying a compressive stress to the plated film by the compressive stress-applying film; and removing the compressive stress-applying film and the plated film which is not buried in the recessed portion.

摘要翻译： 根据本发明的一个方面的制造半导体器件的方法包括在其表面上具有凹陷部分的基板上形成镀膜，以便通过电镀方式将凹陷部分埋入其中; 在电镀膜上形成压缩应力施加膜，该压应力膜由与构成镀膜的金属的热膨胀系数相比具有60％以下的热膨胀系数的材料构成; 通过压应力施加膜向镀膜施加压应力时的热处理; 并且除去未埋设在凹部中的压应力施加膜和镀膜。

公开(公告)号：US06306756B1

公开(公告)日：2001-10-23

申请号：US09580922

申请日：2000-05-26

申请人： Masahiko Hasunuma ,  Sachiyo Ito ,  Keizo Shimamura ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Junsei Tsutsumi ,  Akihiro Kajita ,  Junichi Wada ,  Haruo Okano

发明人： Masahiko Hasunuma ,  Sachiyo Ito ,  Keizo Shimamura ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Junsei Tsutsumi ,  Akihiro Kajita ,  Junichi Wada ,  Haruo Okano

IPC分类号： H01L214763

CPC分类号： H01L21/76882

摘要： A method for the production of a semiconductor device having an electrode line formed in a semiconducting substrate is disclosed which comprises preparing a semiconducting substrate having trenches and/or contact holes formed preparatorily in a region destined to form the electrode line, forming a conductive film formed mainly of at least one member selected from among Cu, Ag, and Au on the surface of the semiconducting substrate, heat-treating the superposed Cu film while supplying at least an oxidizing gas thereto thereby flowing the Cu film and causing never melting to fill the trenches and/or contact holes, and removing by polishing the part of the conductive film which falls outside the region of the electrode line and completing the electrode lines consequently. During the heat treatment, a reducing gas is supplied in addition to the oxidizing gas to induce a local oxidation-reduction reaction and fluidify and/or flow the conductive film and consequently accomplish the embodiment of the conductive film in the trenches. The formation of the interconnection is also accomplished by forming a conductive film on the surface of a semiconducting substrate having trenches formed therein, exerting thereon uniaxial stress from above the semiconducting substrate, heat treating the formed conductive film thereby flowing the conductive film, to fill the trenches, and polishing the surface of the semiconducting substrate.

摘要翻译： 公开了一种制造半导体器件的方法，该半导体器件具有形成在半导体衬底中的电极线，其包括制备半导体衬底，该半导体衬底具有在预定形成电极线的区域中预先形成的沟槽和/或接触孔，形成导电膜 主要是在半导体基板的表面上选自Cu，Ag和Au中的至少一个元件，在至少供给氧化气体的同时对叠加的Cu膜进行热处理，从而使Cu膜流动，从而不会熔化以填充 沟槽和/或接触孔，并且通过抛光导电膜的掉落在电极线的区域外部并且完成电极线的部分去除。 在热处理期间，除了氧化气体之外还提供还原气体以引起局部氧化还原反应，并使导电膜流通和/或流动，从而完成沟槽中导电膜的实施例。 互连的形成还可以通过在其上形成有沟槽的半导体衬底的表面上形成导电膜，在半导体衬底上方施加单轴应力，热处理形成的导电膜从而使导电膜流动，从而填充 沟槽，并抛光半导体衬底的表面。

公开(公告)号：US6090701A

公开(公告)日：2000-07-18

申请号：US521088

申请日：1995-06-20

申请人： Masahiko Hasunuma ,  Sachiyo Ito ,  Keizo Shimamura ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Junsei Tsutsumi ,  Akihiro Kajita ,  Junichi Wada ,  Haruo Okano

发明人： Masahiko Hasunuma ,  Sachiyo Ito ,  Keizo Shimamura ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Junsei Tsutsumi ,  Akihiro Kajita ,  Junichi Wada ,  Haruo Okano

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76882

摘要： A method for the production of a semiconductor device having an electrode line formed in a semiconducting substrate is disclosed which comprises preparing a semiconducting substrate having trenches and/or contact holes formed preparatorily in a region destined to form the electrode line, forming a conductive film formed mainly of at least one member selected from among Cu, Ag, and Au on the surface of the semiconducting substrate, heat-treating the superposed Cu film while supplying at least an oxidizing gas thereto thereby flowing the Cu film to fill the trenches and/or contact holes, and removing by polishing the part of the conductive film which falls outside the region of the electrode line and completing the electrode lines consequently. During the heat treatment, a reducing gas is supplied in addition to the oxidizing gas to induce a local oxidation-reduction reaction and fluidify and/or flow the conductive film and consequently accomplish the embodiment of the conductive film in the trenches.

摘要翻译： 公开了一种制造半导体器件的方法，该半导体器件具有形成在半导体衬底中的电极线，其包括制备半导体衬底，该半导体衬底具有在预定形成电极线的区域中预先形成的沟槽和/或接触孔，形成导电膜 主要是在半导体基板的表面上选自Cu，Ag和Au中的至少一个元件，在至少供给氧化气体的同时对叠加的Cu膜进行热处理，从而使Cu膜流过以填充沟槽和/或 接触孔，并且通过抛光导电膜的掉在电极线的区域外部并且完成电极线的部分去除。 在热处理期间，除了氧化气体之外还提供还原气体以引起局部氧化还原反应，并使导电膜流通和/或流动，从而完成沟槽中导电膜的实施例。