公开(公告)号：US09117885B2

公开(公告)日：2015-08-25

申请号：US13216445

申请日：2011-08-24

申请人： Tatsuro Saito ,  Makoto Wada ,  Akihiro Kajita

发明人： Tatsuro Saito ,  Makoto Wada ,  Akihiro Kajita

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L21/285 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76844 ,  H01L21/28556 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/522 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a graphene interconnection includes a first insulating film, a first catalyst film, and a first graphene layer. A first insulating film includes an interconnection trench. A first catalyst film is formed on the first insulating film on both side surfaces of the interconnection trench. A first graphene layer is formed on the first catalyst film on the both side surfaces of the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to the both side surfaces.

摘要翻译： 根据一个实施例，石墨烯互连包括第一绝缘膜，第一催化剂膜和第一石墨烯层。 第一绝缘膜包括互连沟槽。 在互连沟槽的两个侧表面上的第一绝缘膜上形成第一催化剂膜。 第一石墨烯层形成在互连沟槽的两个侧表面上的第一催化剂膜上，并且包括沿垂直于两个侧表面的方向堆叠的石墨烯片。

公开(公告)号：US08546780B2

公开(公告)日：2013-10-01

申请号：US13022936

申请日：2011-02-08

申请人： Jun Iijima ,  Yasuyoshi Hyodo ,  Akihiro Kajita

发明人： Jun Iijima ,  Yasuyoshi Hyodo ,  Akihiro Kajita

IPC分类号： H01L45/00

CPC分类号： H01L27/2481 ,  H01L27/2409 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/146 ,  H01L45/1675

摘要： According to one embodiment, a non-volatile memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction, and a variable resistance memory cell which is disposed at an intersection between the first wiring and the second wiring so as to be held between the first wiring and the second wiring and includes a variable resistive element and a rectifying element. In a space between the variable resistance memory cells adjacent to each other, at least a periphery of the variable resistive element is evacuated or filled with a gas.

摘要翻译： 根据一个实施例，非易失性存储器件包括沿第一方向延伸的第一布线，沿第二方向延伸的第二布线和布置在第一布线和第二布线之间的交叉点处的可变电阻存储单元 以便保持在第一布线和第二布线之间，并且包括可变电阻元件和整流元件。 在彼此相邻的可变电阻存储单元之间的空间中，可变电阻元件的至少周边被抽气或填充有气体。

公开(公告)号：US20120080662A1

公开(公告)日：2012-04-05

申请号：US13216445

申请日：2011-08-24

申请人： Tatsuro Saito ,  Makoto Wada ,  Akihiro Kajita

发明人： Tatsuro Saito ,  Makoto Wada ,  Akihiro Kajita

IPC分类号： H01L29/15 ,  H01L21/283

CPC分类号： H01L21/76844 ,  H01L21/28556 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/522 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a graphene interconnection includes a first insulating film, a first catalyst film, and a first graphene layer. A first insulating film includes an interconnection trench. A first catalyst film is formed on the first insulating film on both side surfaces of the interconnection trench. A first graphene layer is formed on the first catalyst film on the both side surfaces of the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to the both side surfaces.

摘要翻译： 根据一个实施例，石墨烯互连包括第一绝缘膜，第一催化剂膜和第一石墨烯层。 第一绝缘膜包括互连沟槽。 在互连沟槽的两个侧表面上的第一绝缘膜上形成第一催化剂膜。 第一石墨烯层形成在互连沟槽的两个侧表面上的第一催化剂膜上，并且包括沿垂直于两个侧表面的方向堆叠的石墨烯片。

公开(公告)号：US20110198554A1

公开(公告)日：2011-08-18

申请号：US13022936

申请日：2011-02-08

申请人： Jun Iijima ,  Yasuyoshi Hyodo ,  Akihiro Kajita

发明人： Jun Iijima ,  Yasuyoshi Hyodo ,  Akihiro Kajita

IPC分类号： H01L45/00

CPC分类号： H01L27/2481 ,  H01L27/2409 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/146 ,  H01L45/1675

摘要： According to one embodiment, a non-volatile memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction, and a variable resistance memory cell which is disposed at an intersection between the first wiring and the second wiring so as to be held between the first wiring and the second wiring and includes a variable resistive element and a rectifying element. In a space between the variable resistance memory cells adjacent to each other, at least a periphery of the variable resistive element is evacuated or filled with a gas.

摘要翻译： 根据一个实施例，非易失性存储器件包括沿第一方向延伸的第一布线，沿第二方向延伸的第二布线和布置在第一布线和第二布线之间的交叉点处的可变电阻存储单元 以便保持在第一布线和第二布线之间，并且包括可变电阻元件和整流元件。 在彼此相邻的可变电阻存储单元之间的空间中，可变电阻元件的至少周边被抽气或填充有气体。

公开(公告)号：US20090191712A1

公开(公告)日：2009-07-30

申请号：US12208010

申请日：2008-09-10

申请人： Kazuyuki HIGASHI ,  Takuji Kuniya ,  Makoto Wada ,  Akihiro Kajita

发明人： Kazuyuki HIGASHI ,  Takuji Kuniya ,  Makoto Wada ,  Akihiro Kajita

IPC分类号： H01L21/308

CPC分类号： H01L21/0273 ,  H01L21/0337 ,  H01L21/0338

摘要： In one aspect of the present invention, a method of manufacturing a semiconductor device may include forming a first film on an amorphous silicon layer to be patterned, the first film and the amorphous film having a line-and-space ratio of approximately 3:1, sliming down, after processing the first film, a line portion of the pattern from both longitudinal sides of the line portion until the width of the line portion is reduced to approximately one third, reforming a part of the amorphous silicon layer where the first film is not provided such that reformed part has different etching ratio, and removing the first film and the amorphous silicon layer other than reformed part.

摘要翻译： 在本发明的一个方面中，制造半导体器件的方法可以包括在待图案化的非晶硅层上形成第一膜，第一膜和非线性膜的线间距比约为3:1 ，在对第一膜进行处理之后，将该图案的线部分从线部分的两个纵向侧线直到线部分的宽度减小到大约三分之一，在下一步处理之后，将非晶硅层的一部分重新形成第一膜 不能使重整部分具有不同的蚀刻比，并除去除了重整部分以外的第一膜和非晶硅层。

公开(公告)号：US07215001B2

公开(公告)日：2007-05-08

申请号：US10835594

申请日：2004-04-30

申请人： Akihiro Kajita

发明人： Akihiro Kajita

IPC分类号： H01L21/82 ,  H01L27/10 ,  H01L29/00

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device capable of controlling an operation of a fuse element by increasing a resistance of the fuse element without fusing the fuse wiring by the laser beam irradiation comprises a semiconductor substrate, a first wiring formed above the semiconductor substrate, a second wiring formed above the first wiring, at least one plug which acts as a fuse element to connect the first wiring and the second wiring, and an opening made in a part of an insulator formed above the second wiring so as to correspond to the plug.

摘要翻译： 能够通过增加熔丝元件的电阻而不通过激光束照射熔断熔丝来控制熔丝元件的操作的半导体器件包括半导体衬底，形成在半导体衬底上的第一布线， 第一布线，用作连接第一布线和第二布线的熔丝元件的至少一个插头，以及形成在第二布线上方的绝缘体的一部分中的开口，以对应于插头。

公开(公告)号：US06555925B1

公开(公告)日：2003-04-29

申请号：US09517187

申请日：2000-03-02

申请人： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Akihiro Kajita ,  Tamao Takase ,  Hisashi Kaneko ,  Hideki Shibata

发明人： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Akihiro Kajita ,  Tamao Takase ,  Hisashi Kaneko ,  Hideki Shibata

IPC分类号： H01L23544

CPC分类号： H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is a method of producing a semiconductor device in which at least one alignment mark to be used in an exposure process of a lithographic process is formed of a wiring material which is copper or includes copper as a main component, and the alignment mark is formed entirely in an area outside an area where dicing is to be executed.

摘要翻译： 本发明是一种制造半导体器件的方法，其中在光刻工艺的曝光处理中使用的至少一个对准标记由铜或者铜作为主要成分的布线材料形成，并且对准标记 完全在要执行切割的区域外的区域中形成。

公开(公告)号：US20170229301A9

公开(公告)日：2017-08-10

申请号：US13622089

申请日：2012-09-18

申请人： Masayuki KITAMURA ,  Atsuko SAKATA ,  Makoto WADA ,  Yuichi YAMAZAKI ,  Masayuki KATAGIRI ,  Akihiro KAJITA ,  Tadashi SAKAI ,  Naoshi SAKUMA ,  Ichiro MIZUSHIMA

发明人： Masayuki KITAMURA ,  Atsuko SAKATA ,  Makoto WADA ,  Yuichi YAMAZAKI ,  Masayuki KATAGIRI ,  Akihiro KAJITA ,  Tadashi SAKAI ,  Naoshi SAKUMA ,  Ichiro MIZUSHIMA

IPC分类号： H01L21/28 ,  B82Y40/00

CPC分类号： H01L21/76846 ,  H01L21/02373 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76861 ,  H01L21/76876 ,  H01L23/53276 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

公开(公告)号：US20130217226A1

公开(公告)日：2013-08-22

申请号：US13622089

申请日：2012-09-18

申请人： Masayuki KITAMURA ,  Atsuko SAKATA ,  Makoto WADA ,  Yuichi YAMAZAKI ,  Masayuki KATAGIRI ,  Akihiro KAJITA ,  Tadashi SAKAI ,  Naoshi SAKUMA ,  Ichiro MIZUSHIMA

发明人： Masayuki KITAMURA ,  Atsuko SAKATA ,  Makoto WADA ,  Yuichi YAMAZAKI ,  Masayuki KATAGIRI ,  Akihiro KAJITA ,  Tadashi SAKAI ,  Naoshi SAKUMA ,  Ichiro MIZUSHIMA

IPC分类号： H01L21/28 ,  B82Y40/00

CPC分类号： H01L21/76846 ,  H01L21/02373 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76861 ,  H01L21/76876 ,  H01L23/53276 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

摘要翻译： 根据一个实施例，公开了一种用于制造半导体器件的方法。 该方法包括在半导体衬底的表面上方形成助催化剂层和催化剂层。 助催化剂层和催化剂层具有fcc结构。 fcc结构形成为使得fcc结构的（111）面平行于半导体衬底的表面定向。 催化剂包括与助催化剂层接触的部分。 该部分具有fcc结构。 通过氧化和还原处理使催化剂层的暴露表面平坦化。 在催化剂层上形成石墨烯层。

公开(公告)号：US08487449B2

公开(公告)日：2013-07-16

申请号：US13215463

申请日：2011-08-23

申请人： Makoto Wada ,  Yuichi Yamazaki ,  Masayuki Katagiri ,  Masayuki Kitamura ,  Atsuko Sakata ,  Akihiro Kajita ,  Tadashi Sakai ,  Naohsi Sakuma

发明人： Makoto Wada ,  Yuichi Yamazaki ,  Masayuki Katagiri ,  Masayuki Kitamura ,  Atsuko Sakata ,  Akihiro Kajita ,  Tadashi Sakai ,  Naohsi Sakuma

IPC分类号： H01L29/70 ,  H01L21/4763

CPC分类号： H01L23/53276 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2221/1089 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a carbon nanotube interconnection includes a first conductive layer, an insulating film, a catalyst underlying film, a catalyst deactivation film, a catalyst film, and carbon nanotubes. An insulating film is formed on the first conductive layer and including a hole. An catalyst underlying film is formed on the first conductive layer on a bottom surface in the hole and on the insulating film on a side surface in the hole. A catalyst deactivation film is formed on the catalyst underlying film on the side surface in the hole. A catalyst film is formed on the catalyst underlying film on the bottom surface in the hole and the catalyst deactivation film on the side surface in the hole. Carbon nanotubes are formed in the hole, the carbon nanotubes including one end in contact with the catalyst film on the bottom surface in the hole.

摘要翻译： 根据一个实施例，碳纳米管互连包括第一导电层，绝缘膜，底层催化剂，催化剂失活膜，催化剂膜和碳纳米管。 绝缘膜形成在第一导电层上并包括孔。 在孔的底面上的第一导电层和孔的侧面的绝缘膜上形成催化剂底膜。 在孔中的侧表面上的催化剂底层上形成催化剂失活膜。 在孔的底面的催化剂底层和孔的侧面的催化剂失活膜上形成催化剂膜。 在孔中形成碳纳米管，碳纳米管包括与孔中底表面上的催化剂膜接触的一端。